Datasheet

119
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
• Bit 4:3 – WGM13:2: Waveform Generation Mode
See TCCR1A register description.
• Bit 2:0 – CS12:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see Figure 16-10 on page 114 and
Figure 16-11 on page 115.
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is
configured as an output. This feature allows software control of the counting.
16.11.3 TCCR1C – Timer/Counter1 Control Register C
• Bit 7 – FOC1A: Force Output Compare for Channel A
• Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. When writing a logical one to
the FOC1A/FOC1B bit, an immediate compare match is forced on the waveform generation unit. The OC1A/OC1B output is
changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it
is the value present in the COM1x1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (CTC)
mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero.
Table 16-6. Clock Select Bit Description
CS12 CS11 CS10 Description
0 0 0 No clock source (Timer/Counter stopped).
0 0 1 clk
I/O
/1 (no prescaling)
0 1 0 clk
I/O
/8 (from prescaler)
0 1 1 clk
I/O
/64 (from prescaler)
1 0 0 clk
I/O
/256 (from prescaler)
1 0 1 clk
I/O
/1024 (from prescaler)
1 1 0 External clock source on T1 pin. Clock on falling edge.
1 1 1 External clock source on T1 pin. Clock on rising edge.
Bit 7 6 5 4 3 2 1 0
(0x82) FOC1A FOC1B – – – – – – TCCR1C
Read/Write R/W R/W R R R R R R
Initial Value 0 0 0 0 0 0 0 0