ATmega48PA/ATmega88PA/ATmega168PA 8-bit AVR Microcontroller with 4/8/16K8/16Kbytes In-system DATASHEET Features ● High performance, low power AVR® 8-Bit microcontroller ● Advanced RISC architecture ● ● ● ● ● 131 powerful instructions – most single clock cycle execution 32 8 general purpose working registers Fully static operation Up to 16MIPS throughput at 16MHz On-chip 2-cycle multiplier ● High endurance non-volatile memory segments ● ● ● ● ● 4/8/16K bytes of in-system self-programmable flash program
● I/O and packages ● 23 programmable I/O lines ● 32-lead TQFP, and 32-pad QFN ● Operating voltage: ● 2.7V to 5.5V ● Temperature range: ● –40°C to +125°C ● Speed grade: ● 0 to 8MHz at 2.7V to 5.5V, 0 to 16MHz at 4.5V to 5.5V ● Power consumption ● Active mode: 1.4mA at 4MHz 3V 25°C ● Power-down mode: 0.
1. Pin Configurations Figure 1-1.
1.1 Pin Descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, port B pins that are externally pulled low will source current if the pull-up resistors are activated.
1.1.9 ADC7:6 (TQFP and QFN Package Only) In the TQFP and QFN package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. 2. Overview The Atmel® ATmega48PA/88PA/168PA is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture.
The AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
3. Automotive Quality Grade The Atmel® ATmega48PA/88PA/168PA have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949. This data sheet contains limit values extracted from the results of extensive characterization (temperature and voltage). The quality and reliability of the Atmel ATmega48PA/88PA/168PA have been verified during regular product qualification as per AEC-Q100 grade 1 (–40°C to +125°C). Table 3-1. 4.
7. AVR CPU Core 7.1 Overview This section discusses the AVR® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 7-1.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR® instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program flash memory space is divided in two sections, the boot program section and the application program section. Both sections have dedicated lock bits for write and read/write protection.
• Bit 5 – H: Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. Half carry Is useful in BCD arithmetic. See Section 32. “Instruction Set Summary” on page 317 for detailed information. • Bit 4 – S: Sign Bit, S = N Å V The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See Section 32. “Instruction Set Summary” on page 317 for detailed information.
7.4 General Purpose Register File The register file is optimized for the AVR® enhanced RISC instruction set.
7.4.1 The X-Register, Y-Register, and Z-Register The registers R26...R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3. Figure 7-3.
7.5.1 7.
7.7 Reset and Interrupt Handling The AVR® provides several different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in the status register in order to enable the interrupt.
Assembly Code Example in cli sbi sbi out r16, SREG ; store SREG value ; disable interrupts during timed sequence EECR, EEMPE ; start EEPROM write EECR, EEPE SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<
8. AVR Memories 8.1 Overview This section describes the different memories in the Atmel® ATmega48PA/88PA/168PA. The AVR® architecture has two main memory spaces, the data memory and the program memory space. In addition, the Atmel ATmega48PA/88PA/168PA features an EEPROM memory for data storage. All three memory spaces are linear and regular. 8.
Figure 8-2. Program Memory Map Atmel ATmega88PA, Atmel ATmega168PA Program Memory 0x0000 Application Flash Section Boot Flash Section 0x3FFF/0x1FFF/0x3FFF 8.3 SRAM Data Memory Figure 8-3 shows how the Atmel® ATmega48PA/88PA/168PA SRAM memory is organized. The Atmel ATmega48PA/88PA/168PA is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the opcode for the IN and OUT instructions.
8.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 8-4. Figure 8-4. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Data Write WR Data Read RD Memory Access Instruction 8.4 Next Instruction EEPROM Data Memory The Atmel® ATmega48PA/88PA/168PA contains 256/512/512 bytes of data EEPROM memory.
8.4.2 Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly.
8.6 Register Description 8.6.
Table 8-1. EEPROM Mode Bits EEPM1 EEPM0 Programming Time Operation 0 0 3.4ms Erase and write in one operation (atomic operation) 0 1 1.8ms Erase only 1 0 1.8ms Write only 1 1 – Reserved for future use • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM ready interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM ready interrupt generates a constant interrupt when EEPE is cleared.
The calibrated oscillator is used to time the EEPROM accesses. Table 8-2 lists the typical programming time for EEPROM access from the CPU. Table 8-2. EEPROM Programming Time Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time 26,368 3.3ms EEPROM write (from CPU) The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g.
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
9. System Clock and Clock Options 9.1 Clock Systems and their Distribution Figure 9-1 presents the principal clock systems in the AVR® and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in Section 10. “Power Management and Sleep Modes” on page 35. The clock systems are detailed below. Figure 9-1.
9.1.3 Flash Clock – clkFLASH The flash clock controls operation of the flash interface. The flash clock is usually active simultaneously with the CPU clock. 9.1.4 Asynchronous Timer Clock – clkASY The asynchronous timer clock allows the asynchronous Timer/Counter to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. 9.1.
Main purpose of the delay is to keep the AVR® in reset until it is supplied with minimum VCC. The delay will not monitor the actual voltage and it will be required to select a delay longer than the VCC rise time. If this is not possible, an internal or external brown-out detection circuit should be used. A BOD circuit will ensure sufficient VCC before it releases the reset, and the time-out delay can be disabled.
The CKSEL0 Fuse together with the SUT1...0 fuses select the start-up times as shown in Table 9-4 on page 27. Table 9-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1...0 Ceramic resonator, fast rising power 258CK 14CK + 4.
Figure 9-3. Crystal Oscillator Connections C2 XTAL2 (TOSC2) C1 XTAL1 (TOSC1) GND Table 9-6. Start-up Times for the Full Swing Crystal Oscillator Clock Selection Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1...0 Ceramic resonator, fast rising power 258CK 14CK + 4.
The low-frequency crystal oscillator provides an internal load capacitance, see Table 9-8 at each TOSC pin. Table 9-8. Capacitance for Low-frequency Oscillator Device Atmel ATmega48PA/88PA/168PA 32kHz Osc. Type Cap(Xtal1/Tosc1) Cap(Xtal2/Tosc2) System Osc. 18pF 8pF Timer Osc.
9.6 Calibrated Internal RC Oscillator By default, the internal RC oscillator provides an approximate 8.0MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See Table 29-3 on page 271 for more details. The device is shipped with the CKDIV8 Fuse programmed. See Section 9.11 “System Clock Prescaler” on page 32 for more details. This clock may be selected as the system clock by programming the CKSEL fuses as shown in Table 9-1 on page 25.
When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 9-14. Table 9-14. Start-up Times for the 128kHz Internal Oscillator Note: 9.8 Power Conditions Start-up Time from Power-down and Power-save Additional Delay from Reset SUT1...0 BOD enabled 6CK 14CK(1) 00 Fast rising power 6CK 14CK + 4ms 01 Slowly rising power 6CK 14CK + 64ms 10 1. Reserved If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4.
9.9 Clock Output Buffer The device can output the system clock on the CLKO pin. To enable the output, the CKOUT fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. The clock also will be output during reset, and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC oscillator, can be selected when the clock is output on CLKO.
9.12 Register Description 9.12.1 OSCCAL – Oscillator Calibration Register Bit 7 6 5 4 3 2 1 0 (0x66) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7:0 – CAL[7:0]: Oscillator Calibration Value The oscillator calibration register is used to trim the calibrated internal RC oscillator to remove process variations from the oscillator frequency.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting.
10. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR® provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. When enabled, the brown-out detector (BOD) actively monitors the power supply voltage during the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes. See Section 10.2 “BOD Disable(1)” on page 36 for more details.
10.2 BOD Disable(1) When the brown-out detector (BOD) is enabled by BODLEVEL fuses - see Table 28-6 on page 253 and onwards, the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the BOD by software for some of the sleep modes, see Table 10-1 on page 35. The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses.
10.6 Power-save Mode When the SM2...0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-save mode. This mode is identical to power-down, with one exception: If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from either timer overflow or output compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the global interrupt enable bit in SREG is set.
10.10.3 Brown-out Detector If the brown-out detector is not needed by the application, this module should be turned off. If the brown-out detector is enabled by the BODLEVEL fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to Section 11.5 “Brown-out Detection” on page 43 for details on how to configure the brown-out detector. 10.10.
Table 10-2. Sleep Mode Select SM2 SM1 SM0 Sleep Mode 0 0 0 Idle 0 0 1 ADC Noise Reduction 0 1 0 Power-down 0 1 1 Power-save 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Standby(1) Note: 1 1. 1 1 External Standby(1) Standby mode is only recommended for use with external crystals or resonators. • Bit 0 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.
10.11.3 PRR – Power Reduction Register Bit 7 6 5 4 3 2 1 0 (0x64) PRTWI PRTIM2 PRTIM0 – PRTIM1 PRSPI PRUSART0 PRADC Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PRR • Bit 7 – PRTWI: Power Reduction TWI Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation.
11. System Control and Reset 11.1 Resetting the AVR During reset, all I/O registers are set to their initial values, and the program starts execution from the reset vector. For Atmel® ATmega168PA the instruction placed at the reset vector must be a JMP – absolute jump – instruction to the reset handling routine. For the Atmel ATmega48PA and Atmel ATmega88PA, the instruction placed at the reset vector must be an RJMP – relative jump – instruction to the reset handling routine.
Figure 11-1. Reset Logic DATA BUS WDRF BORF EXTRF PORF MCU Status Register (MCUSR) Power-on Reset Circuit VCC Pull-up Resistor Reset Circuit S Watchdog Timer SPIKE FILTER RESET COUNTER RESET R RSTDISBL Q INTERNAL RESET Brown-out Reset Circuit BODLEVEL [2..0] Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 11.3 Power-on Reset A power-on reset (POR) pulse is generated by an on-chip detection circuit. The detection level is defined in Section 29.
Figure 11-3. MCU Start-up, RESET Extended Externally V POT VCC V RST RESET tTOUT TIME-OUT INTERNAL RESET 11.4 External Reset An external reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Section 29.5 “System and Reset Characteristics” on page 272) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
11.6 Watchdog System Reset When the watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the time-out period tTOUT. Refer to Section 11.8 “Watchdog Timer” on page 45 for details on operation of the watchdog timer. Figure 11-6. Watchdog System Reset During Operation VCC RESET 1 CK Cycle WDT TIME-OUT RESET Time-OUT tTOUT INTERNAL RESET 11.
11.8 Watchdog Timer 11.8.1 Features ● ● ● ● Clocked from separate on-chip oscillator 3 Operating modes ● Interrupt ● System reset ● Interrupt and system reset Selectable time-out period from 16ms to 8s Possible hardware fuse watchdog always on (WDTON) for fail-safe mode 11.8.2 Overview The Atmel ATmega48PA/88PA/168PA has an enhanced watchdog timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128kHz oscillator.
The following code example shows one assembly and one C function for turning off the watchdog timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.
The following code example shows one assembly and one C function for changing the time-out value of the watchdog timer. Assembly Code Example(1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence lds r16, WDTCSR ori r16, (1<
11.9 Register Description 11.9.1 MCUSR – MCU Status Register The MCU status register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 0x34 (0x54) – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description • Bit 7:4: Reserved These bits are unused bits in the Atmel® ATmega48PA/88PA/168PA, and will always read as zero.
Table 11-1. Watchdog Timer Configuration WDTON(1) WDE WDIE 1 0 1 Mode Action on Time-out 0 Stopped None 0 1 Interrupt Mode Interrupt 1 1 0 System Reset Mode Reset 1 1 1 Interrupt and System Reset Mode Interrupt, then go to System Reset Mode 0 Note: 1. x x System Reset Mode Reset WDTON fuse set to “0” means programmed and “1” means unprogrammed. • Bit 4 – WDCE: Watchdog Change Enable This bit is used in timed sequences for changing WDE and prescaler bits.
12. Interrupts This section describes the specifics of the interrupt handling as performed in the Atmel® ATmega48PA/88PA/168PA. For a general explanation of the AVR® interrupt handling, refer to Section 7.7 “Reset and Interrupt Handling” on page 14.
The most typical and general program setup for the reset and interrupt vector addresses in Atmel® ATmega48PA is: Address Labels Code Comments 0x000 rjmp RESET ; Reset Handler 0x001 rjmp EXT_INT0 ; IRQ0 Handler 0x002 rjmp EXT_INT1 ; IRQ1 Handler 0x003 rjmp PCINT0 ; PCINT0 Handler 0x004 rjmp PCINT1 ; PCINT1 Handler 0x005 rjmp PCINT2 ; PCINT2 Handler 0x006 rjmp WDT ; Watchdog Timer Handler 0x007 rjmp TIM2_COMPA ; Timer2 Compare A Handler 0x008 rjmp TIM2_COMPB ; Timer2 Compare B Handler 0x009 rjmp TIM2_OVF ; Ti
12.2 Interrupt Vectors in the Atmel ATmega88PA Table 12-2. Reset and Interrupt Vectors in the Atmel ATmega88PA Vector No.
Table 12-3 shows reset and interrupt vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. This is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. Table 12-3.
When the BOOTRST fuse is unprogrammed, the boot section size set to 2K bytes and the IVSEL bit in the MCUCR register is set before any interrupts are enabled, the most typical and general program setup for the reset and interrupt vector addresses in the Atmel® ATmega88PA is: Address Labels Code Comments 0x000 RESET: ldi r16,high(RAMEND); Main program start 0x001 out SPH,r16 ; Set Stack Pointer to top of RAM 0x002 ldi r16,low(RAMEND) 0x003 out SPL,r16 0x004 sei ; Enable interrupts 0x005 xxx ; .
12.3 Interrupt Vectors in the Atmel ATmega168PA Table 12-4. Reset and Interrupt Vectors in the Atmel ATmega168PA Vector No.
Table 12-5 shows reset and interrupt vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. This is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. Table 12-5.
When the BOOTRST fuse is unprogrammed, the boot section size set to 2Kbytes and the IVSEL bit in the MCUCR register is set before any interrupts are enabled, the most typical and general program setup for the reset and interrupt vector addresses in the Atmel® ATmega168PA is: Address Labels Code Comments 0x0000 RESET: ldi r16,high(RAMEND); Main program start 0x0001 out SPH,r16 ; Set Stack Pointer to top of RAM 0x0002 ldi r16,low(RAMEND) 0x0003 out SPL,r16 0x0004 sei ; Enable interrupts 0x0005 xxx ; .
12.4 Register Description 12.4.1 Moving Interrupts Between Application and Boot Space, Atmel ATmega88PA, ATmega168PA The MCU control register controls the placement of the interrupt vector table.
13. External Interrupts The external interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23...0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23...0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI2 will trigger if any enabled PCINT[23:16] pin toggles. The pin change interrupt PCI1 will trigger if any enabled PCINT[14:8] pin toggles.
13.2 Register Description 13.2.1 EICRA – External Interrupt Control Register A The external interrupt control register A contains control bits for interrupt sense control. Bit 7 6 5 4 3 2 1 0 (0x69) – – – – ISC11 ISC10 ISC01 ISC00 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EICRA • Bit 7:4 – Reserved These bits are unused bits in the Atmel® ATmega48PA/88PA/168PA, and will always read as zero.
13.2.2 EIMSK – External Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 0x1D (0x3D) – – – – – – INT1 INT0 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 EIMSK • Bit 7:2 – Reserved These bits are unused bits in the Atmel® ATmega48PA/88PA/168PA, and will always read as zero. • Bit 1 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the status register (SREG) is set (one), the external pin interrupt is enabled.
13.2.4 PCICR – Pin Change Interrupt Control Register Bit 7 6 5 4 3 2 1 0 (0x68) – – – – – PCIE2 PCIE1 PCIE0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCICR • Bit 7:3 – Reserved These bits are unused bits in the Atmel® ATmega48PA/88PA/168PA, and will always read as zero. • Bit 2 – PCIE2: Pin Change Interrupt Enable 2 When the PCIE2 bit is set (one) and the I-bit in the status register (SREG) is set (one), pin change interrupt 2 is enabled.
13.2.6 PCMSK2 – Pin Change Mask Register 2 Bit (0x6D) 7 6 5 4 3 2 1 0 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK2 • Bit 7:0 – PCINT[23:16]: Pin Change Enable Mask 23...16 Each PCINT[23:16]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
14. I/O-Ports 14.1 Overview All AVR® ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
14.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 14-2 shows a functional description of one I/Oport pin, here generically called Pxn. Figure 14-2. General Digital I/O(1) PUD Q D DDxn Q CLR RESET WDx RDx 0 PORTxn Q CLR RESET SLEEP DATA BUS 1 D Q Pxn WRx WPx RRx Synchronizer RPx D Q D Q PINxn L Q Q CLKI/O PUD: SLEEP: CLKI/O: Note: 1.
14.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 14.2.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur.
When reading back a software assigned pin value, a nope instruction must be inserted as indicated in Figure 14-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. Figure 14-4.
14.2.5 Digital Input Enable and Sleep Modes As shown in Figure 14-2 on page 65, the digital input signal can be clamped to ground at the input of the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU sleep controller in power-down mode, power-save mode, and standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins.
Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 14-5 shows how the port pin control signals from the simplified Figure 14-2 on page 65 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR® microcontroller family. Figure 14-5.
Table 14-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 14-5 on page 69 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 14-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE If this signal is set, the pull-up enable is controlled by the PUOV signal.
14.3.1 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 14-3. Table 14-3.
• SCK/PCINT5 – Port B, Bit 5 SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB5. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit. PCINT5: Pin change interrupt source 5. The PB5 pin can serve as an external interrupt source.
Table 14-4 and Table 14-5 relate the alternate functions of port B to the overriding signals shown in Figure 14-5. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. Table 14-4. Overriding Signals for Alternate Functions in PB7...
14.3.2 Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 14-6. Table 14-6.
• ADC3/PCINT11 – Port C, Bit 3 PC3 can also be used as ADC input channel 3. Note that ADC input channel 3 uses analog power. PCINT11: Pin change interrupt source 11. The PC3 pin can serve as an external interrupt source. • ADC2/PCINT10 – Port C, Bit 2 PC2 can also be used as ADC input channel 2. Note that ADC input channel 2 uses analog power. PCINT10: Pin change interrupt source 10. The PC2 pin can serve as an external interrupt source.
Table 14-8. Overriding Signals for Alternate Functions in PC3...
• AIN0/OC0A/PCINT22 – Port D, Bit 6 AIN0, analog comparator positive input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. OC0A, output compare match output: The PD6 pin can serve as an external output for the Timer/Counter0 compare match A. The PD6 pin has to be configured as an output (DDD6 set (one)) to serve this function.
Table 14-10 and Table 14-11 relate the alternate functions of port D to the overriding signals shown in Figure 14-5 on page 69. Table 14-10. Overriding Signals for Alternate Functions PD7...
14.4 Register Description 14.4.1 MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) – BODS(1) BODSE(1) PUD – – IVSEL IVCE Read/Write R R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: 1.
14.4.7 PINC – The Port C Input Pins Address Bit 7 6 5 4 3 2 1 0 0x06 (0x26) – PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 Read/Write R R R R R R R R Initial Value 0 N/A N/A N/A N/A N/A N/A N/A 4 3 2 1 0 PINC 14.4.8 PORTD – The Port D Data Register Bit 0x0B (0x2B) 7 6 5 PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PORTD 14.4.
15. 8-bit Timer/Counter0 with PWM 15.1 Features ● ● ● ● ● ● ● Double buffered output compare registers Clear timer on compare match (auto reload) Glitch free, phase correct pulse width modulator (PWM) Variable PWM period Frequency generator Three independent interrupt sources (TOV0, OCF0A, and OCF0B) Overview Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent output compare Units, and with PWM support.
15.2.1 Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the output compare Unit, in this case compare unit A or compare unit B. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on. The definitions in Table 15-1 are also used extensively throughout the document.
15.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 15-2 shows a block diagram of the counter and its surroundings. Figure 15-2. Counter Unit Block Diagram TOVn (Int. Req.) DATA BUS Clock Select count clear TCNTn Edge Detector clkTn Control Logic Tn direction (from Prescaler) bottom top Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement.
15.5 Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the output compare registers (OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the output compare flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. The output compare flag is automatically cleared when the interrupt is executed.
15.5.3 Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the output compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting.
15.6.1 Compare Output Mode and Waveform Generation The waveform generator uses the COM0x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the waveform generator that no action on the OC0x register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 15-2 on page 91. For fast PWM mode, refer to Table 15-3 on page 92, and for phase correct PWM refer to Table 15-4 on page 92.
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature.
The Timer/Counter overflow flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
Figure 15-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter overflow flag (TOV0) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
15.8 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set. Figure 15-8 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 15-8.
Figure 15-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP. Figure 15-11.Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC) TOP - 1 TOP OCRnx BOTTOM BOTTOM + 1 TOP OCFnx 15.9 Register Description 15.9.
Table 15-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode. Table 15-3. Compare Output Mode, Fast PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal port operation, OC0A disconnected. WGM02 = 1: Toggle OC0A on compare match. 1 0 Clear OC0A on compare match, set OC0A at BOTTOM, (non-inverting mode). 1 Note: 1. Description Set OC0A on compare match, clear OC0A at BOTTOM, (inverting mode).
Table 15-6 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM mode. Table 15-6. Compare Output Mode, Fast PWM Mode(1) COM0B1 COM0B0 Description 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on compare match, set OC0B at BOTTOM,(non-inverting mode) Note: 1 1. 1 Set OC0B on compare match, clear OC0B at BOTTOM,(inverting mode). A special case occurs when OCR0B equals TOP and COM0B1 is set.
15.9.2 TCCR0B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 0x25 (0x45) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
15.9.3 TCNT0 – Timer/Counter Register Bit 7 6 5 0x26 (0x46) 4 3 2 1 0 TCNT0[7:0] TCNT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Timer/Counter register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock.
15.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x15 (0x35) – – – – – OCF0B OCF0A TOV0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR0 • Bits 7:3 – Reserved These bits are reserved bits in the Atmel® ATmega48PA/88PA/168PA and will always read as zero.
16. 16-bit Timer/Counter1 with PWM 16.1 Features ● ● ● ● ● ● ● ● ● ● ● 16.2 True 16-bit design (i.e.
Figure 16-1. 16-bit Timer/Counter Block Diagram(1) TOVn (Int. Req.) Count Clear Direction Clock Select Control Logic clkTn TOP BOTTOM = = Edge Detector Tn (from Prescaler) Timer/Counter TCNTn 0 OCnA (Int. Req.) Waveform Generation = OCnA OCRnA DATA BUS Fixed TOP Values OCnB (Int. Req.) Waveform Generation = OCRnB OCnB (From Analog Comparator Output) ICFn (Int. Req.) Edge Detector ICRn TCCRnA Note: 98 1.
16.2.1 Registers The Timer/Counter (TCNT1), output compare registers (OCR1A/B), and input capture register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the Section 16.3 “Accessing 16-bit Registers” on page 100. The Timer/Counter control registers (TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req.
16.3 Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR® CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation.
The following code examples show how to do an atomic read of the TCNT1 register contents. Reading any of the OCR1A/B or ICR1 registers can be done by using the same principle.
The following code examples show how to do an atomic write of the TCNT1 register contents. Writing any of the OCR1A/B or ICR1 registers can be done by using the same principle.
16.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 16-2 shows a block diagram of the counter and its surroundings. Figure 16-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int. Req.
16.6 Input Capture Unit The Timer/Counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events.
16.6.1 Input Capture Trigger Source The main trigger source for the input capture unit is the input capture pin (ICP1). Timer/Counter1 can alternatively use the analog comparator output as trigger source for the input capture unit. The analog comparator is selected as trigger source by setting the analog comparator input capture (ACIC) bit in the analog comparator control and status register (ACSR). Be aware that changing trigger source can trigger a capture.
Figure 16-4 shows a block diagram of the output compare unit. The small “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates output compare unit (A/B). The elements of the block diagram that are not directly a part of the output compare unit are gray shaded. Figure 16-4. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf.
16.7.2 Compare Match Blocking by TCNT1 Write All CPU writes to the TCNT1 register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled. 16.7.
The general I/O port function is overridden by the output compare (OC1x) from the waveform generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the data direction register (DDR) for the port pin. The data direction register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visible on the pin. The port override function is generally independent of the waveform generation mode, but there are some exceptions.
16.9.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency.
16.9.3 Fast PWM Mode The fast pulse width modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting compare output mode, the output compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x, and set at BOTTOM.
The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 register is not double buffered. This means that if ICR1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICR1 value written is lower than the current value of TCNT1. The result will then be that the counter will miss the compare match at the TOP value.
In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 16-8 on page 112.
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
The Timer/Counter overflow flag (TOV1) is set at the same timer clock cycle as the OCR1x registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag set when TCNT1 has reached TOP. The interrupt flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value.
Figure 16-11 shows the same timing data, but with the prescaler enabled. Figure 16-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) OCRnx - 1 TCNTn OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 16-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x register is updated at BOTTOM.
Figure 16-13 shows the same timing data, but with the prescaler enabled. Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value 16.11 Register Description 16.11.
Table 16-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 16-3. Compare Output Mode, Fast PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 14 or 15: Toggle OC1A on compare match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.
Table 16-5.
• Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A register description. • Bit 2:0 – CS12:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter, see Figure 16-10 on page 114 and Figure 16-11 on page 115. Table 16-6. Clock Select Bit Description CS12 CS11 CS10 Description 0 0 0 No clock source (Timer/Counter stopped).
16.11.4 TCNT1H and TCNT1L – Timer/Counter1 Bit 7 6 5 4 3 (0x85) TCNT1[15:8] (0x84) TCNT1[7:0] 2 1 0 TCNT1H TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter.
16.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x6F) – – ICIE1 – – OCIE1B OCIE1A TOIE1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK1 • Bit 7, 6 – Reserved These bits are unused bits in the Atmel® ATmega48PA/88PA/168PA, and will always read as zero.
• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the output compare register B (OCR1B). Note that a forced output compare (FOC1B) strobe will not set the OCF1B flag. OCF1B is automatically cleared when the output compare match B interrupt vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
17. Timer/Counter0 and Timer/Counter1 Prescalers Section 15. “8-bit Timer/Counter0 with PWM” on page 81 and Section 16. “16-bit Timer/Counter1 with PWM” on page 97 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 17.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
Figure 17-2. Prescaler for Timer/Counter0 and Timer/Counter1(1) CK/64 CK/8 PSRSYNC Note: 17.4 T0 Synchronization T1 Synchronization 1. 0 CK/1024 10-bit T/C Prescaler Clear CK/256 clkI/O 0 CS10 CS00 CS11 CS01 CS12 CS02 Timer/Counter 1Clock Source Timer/Counter 0 Clock Source clkT1 clkT0 The synchronization logic on the input pins (T1/T0) is shown in Figure 17-1. Register Description 17.4.
18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 18.1 Features ● ● ● ● ● ● ● Clear timer on compare match (auto reload) Glitch-free, phase correct pulse width modulator (PWM) Frequency generator 10-bit Clock prescaler Overflow and compare match interrupt sources (TOV2, OCF2A and OCF2B) Allows clocking from external 32kHz watch crystal independent of the I/O clock Overview Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module.
18.2.1 Registers The Timer/Counter (TCNT2) and output compare register (OCR2A and OCR2B) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the timer interrupt flag register (TIFR2). All interrupts are individually masked with the timer interrupt mask register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section.
18.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 18-2 shows a block diagram of the counter and its surrounding environment. Figure 18-2. Counter Unit Block Diagram TOVn (Int. Req.) DATA BUS TOSC1 T/C Oscillator count clear TCNTn Control Logic clkTn Prescaler TOSC2 direction clkI/O bottom top Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement.
18.5 Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the output compare register (OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a match. A match will set the output compare flag (OCF2A or OCF2B) at the next timer clock cycle. If the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. The output compare flag is automatically cleared when the interrupt is executed.
18.5.3 Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the output compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting.
18.6.1 Compare Output Mode and Waveform Generation The waveform generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1:0 = 0 tells the waveform generator that no action on the OC2x register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 18-5 on page 138. For fast PWM mode, refer to Table 18-6 on page 138, and for phase correct PWM refer to Table 18-7 on page 139.
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. (See Table 18-3 on page 137). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output.
The Timer/Counter overflow flag (TOV2) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2x1:0 to three.
Figure 18-9 shows the same timing data, but with the prescaler enabled. Figure 18-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 18-10 shows the setting of OCF2A in all modes except CTC mode. Figure 18-10.
18.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. ● Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the timer registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is: ● ● a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2. b. Select clock source by setting AS2 as appropriate. c.
● Reading of the TCNT2 register shortly after wake-up from power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from powersave mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge.
18.11 Register Description 18.11.1 TCCR2A – Timer/Counter Control Register A Bit 7 (0xB0) 6 5 4 COM2A1 COM2A0 COM2B1 COM2B0 3 2 1 0 – – WGM21 WGM20 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR2A • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the output compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to.
Table 18-4 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Table 18-4. Compare Output Mode, Phase Correct PWM Mode(1) COM2A1 COM2A0 0 0 Normal port operation, OC2A disconnected. 0 1 WGM22 = 0: Normal port operation, OC2A disconnected. WGM22 = 1: Toggle OC2A on compare match. 1 0 Clear OC2A on compare match when up-counting. Set OC2A on compare match when down-counting. 1 Note: 1. Description Set OC2A on compare match when up-counting.
Table 18-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Table 18-7. Compare Output Mode, Phase Correct PWM Mode(1) COM2B1 COM2B0 0 0 Normal port operation, OC2B disconnected. 0 1 Reserved 1 0 Clear OC2B on compare match when up-counting. Set OC2B on compare match when down-counting. 1 Note: 1. Description Set OC2B on compare match when up-counting. Clear OC2B on compare match when down-counting.
18.11.2 TCCR2B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 (0xB1) FOC2A FOC2B – – WGM22 CS22 CS21 CS20 Read/Write W W R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR2B • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode.
18.11.3 TCNT2 – Timer/Counter Register Bit 7 6 5 4 (0xB2) 3 2 1 0 TCNT2[7:0] TCNT2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Timer/Counter register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the compare match on the following timer clock.
18.11.7 TIFR2 – Timer/Counter2 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x17 (0x37) – – – – – OCF2B OCF2A TOV2 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR2 • Bit 2 – OCF2B: Output Compare Flag 2 B The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B – output compare register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling vector.
• Bit 2 – OCR2BUB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value. • Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set.
19. SPI – Serial Peripheral Interface 19.1 Features ● ● ● ● ● ● ● ● 19.
The interconnection between master and slave CPUs with SPI is shown in Figure 19-2 on page 145. The system consists of two shift registers, and a master clock generator. The SPI master initiates the communication cycle when pulling low the slave select SS pin of the desired slave. master and slave prepare the data to be sent in their respective shift registers, and the master generates the required clock pulses on the SCK line to interchange data.
The following code examples show how to initialize the SPI as a master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual data direction register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
19.3 SS Pin Functionality 19.3.1 Slave Mode When the SPI is configured as a slave, the slave select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
Figure 19-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD =1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 19-4.
19.5 Register Description 19.5.1 SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the global interrupt enable bit in SREG is set.
Table 19-5. Relationship Between SCK and the Oscillator Frequency SPI2X SPR1 SPR0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 SCK Frequency fosc/4 fosc/16 fosc/64 fosc/128 fosc/2 fosc/8 fosc/32 fosc/64 19.5.
20. USART0 20.1 Features ● ● ● ● ● ● ● ● ● ● ● ● 20.
Figure 20-1. USART Block Diagram(1) Clock Generator UBRRn [H:L] OSC Baud Rate Generator Sync Logic Pin Control XCKn Transmitter TX Control DATA BUS UDRn (Transmit) Parity Generator 20.3 1. TxDn Receiver Clock Recovery RX Control Receive Shift Register Data Recovery Pin Control UDRn (Receive) Parity Checker UCSRnA Note: Pin Control Transmit Shift Register UCSRnB RxDn UCSRnC Refer to Figure 1-1 on page 3 and Table 14-9 on page 76 for USART0 pin placement.
Figure 20-2 shows a block diagram of the clock generation logic. Figure 20-2. Clock Generation Logic, Block Diagram UBRRn U2Xn foscn Prescaling Down-Counter UBRRn+1 /2 /4 /2 0 1 OSC 0 DDR_XCKn xcki XCKn Pin Sync Register Edge Detector xcko DDR_XCKn 1 0 UMSELn 1 UCPOLn txclk 0 1 rxclk Signal description: txclk Transmitter clock (internal signal). rxclk Receiver base clock (internal signal). xcki Input from XCK pin (internal signal). Used for synchronous slave operation.
Table 20-1 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRRn value for each mode of operation using an internally generated clock source. Table 20-1.
20.3.4 Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input (slave) or clock output (master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxDn) is sampled at the opposite XCKn clock edge of the edge the data output (TxDn) is changed. Figure 20-3.
The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The receiver and transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the receiver and transmitter. The USART character size (UCSZn2:0) bits select the number of data bits in the frame. The USART parity mode (UPMn1:0) bits enable and set the type of parity bit.
Assembly Code Example(1) USART_Init: ; Set baud rate out UBRRnH, r17 out UBRRnL, r16 ; Enable receiver and transmitter ldi r16, (1<
20.6 Data Transmission – The USART Transmitter The USART transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB register. When the transmitter is enabled, the normal port operation of the TxDn pin is overridden by the USART and given the function as the transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
20.6.2 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCSRnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
20.6.3 Transmitter Flags and Interrupts The USART transmitter has two flags that indicate its state: USART data register empty (UDREn) and transmit complete (TXCn). Both flags can be used for generating interrupts. The data register empty (UDREn) Flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the shift register.
The following code example shows a simple USART receive function based on polling of the receive complete (RXCn) flag. When using frames with less than eight bits the most significant bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used.
Assembly Code Example(1) USART_Receive: ; Wait for data to be received in r16, UCSRnA sbrs r16, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRnA in r17, UCSRnB in r16, UDRn ; If error, return -1 andi r18,(1<
20.7.4 Receiver Error Flags The USART receiver has three error flags: frame error (FEn), data overrun (DORn) and parity error (UPEn). All can be accessed by reading UCSRnA. Common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the error flags, the UCSRnA must be read before the receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location.
20.7.7 Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the receiver is disabled, i.e., the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDRn I/O location until the RXCn flag is cleared. The following code example shows how to flush the receive buffer.
When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and samples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the figure), to decide if a valid start bit is received.
20.8.3 Asynchronous Operational Range The operational range of the receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. If the transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the receiver does not have a similar (see Table 20-2 on page 167) base frequency, the receiver will not be able to synchronize the frames to the start bit.
20.9 Multi-processor Communication Mode Setting the multi-processor communication mode (MPCMn) bit in UCSRnA enables a filtering function of incoming frames received by the USART receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU, in a system with multiple MCUs that communicate via the same serial bus.
Table 20-4. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies fosc = 1.0000MHz Baud Rate (bps) U2Xn = 0 fosc = 1.8432MHz U2Xn = 1 U2Xn = 0 fosc = 2.0000MHz U2Xn = 1 U2Xn = 0 U2Xn = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 –7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.
Table 20-6. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592MHz fosc = 8.0000MHz fosc = 14.7456MHz Baud Rate (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 207 0.2% 416 –0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 –0.8% 68 0.6% 47 0.0% 95 0.
20.11 Register Description 20.11.1 UDRn – USART I/O Data Register n Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDRn (Read) TXB[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART transmit data buffer register and USART receive data buffer registers share the same I/O address referred to as USART data register or UDRn. The transmit data buffer register (TXB) will be the destination for data written to the UDRn register location.
• Bit 2 – UPEn: USART Parity Error This bit is set if the next character in the receive buffer had a parity error when received and the parity checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA. • Bit 1 – U2Xn: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation.
• Bit 0 – TXB8n: Transmit Data Bit 8 n TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDRn. 20.11.
Table 20-11. UCSZn Bits Settings UCSZn2 UCSZn1 UCSZn0 Character Size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9-bit • Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn). Table 20-12.
21. USART in SPI Mode 21.1 Features ● ● ● ● ● ● ● ● 21.
21.4 SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in Figure 21-1. Data bits are shifted out and latched in on opposite edges of the XCKn signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn functionality is summarized in Table 21-2.
21.5.1 USART MSPIM Initialization The USART in MSPIM mode has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting master mode of operation (by setting DDR_XCKn to one), setting frame format and enabling the transmitter and the receiver. Only the transmitter can operate independently.
21.6 Data Transfer Using the USART in MSPI mode requires the transmitter to be enabled, i.e. the TXENn bit in the UCSRnB register is set to one. When the transmitter is enabled, the normal port operation of the TxDn pin is overridden and given the function as the transmitter's serial output. Enabling the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one.
21.6.1 Transmitter and Receiver Flags and Interrupts The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode are identical in function to the normal USART operation. However, the receiver error status flags (FE, DOR, and PE) are not in use and is always read as zero. 21.6.2 Disabling the Transmitter or Receiver The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to the normal USART operation. 21.
• Bit 7 – RXCn: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive buffer will be flushed and consequently the RXCn bit will become zero. The RXCn flag can be used to generate a receive complete interrupt (see description of the RXCIEn bit).
21.8.4 UCSRnC – USART MSPIM Control and Status Register n C Bit 7 6 5 4 3 2 1 0 UMSELn1 UMSELn0 – – – UDORDn UCPHAn UCPOLn Read/Write R/W R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 1 1 0 UCSRnC • Bit 7:6 – UMSELn1:0: USART Mode Select These bits select the mode of operation of the USART as shown in Table 21-4. See Section 20.11.4 “UCSRnC – USART Control and Status Register n C” on page 173 for full description of the normal USART operation.
22. 2-wire Serial Interface 22.1 Features ● ● ● ● ● ● ● ● ● ● ● 22.
22.2.2 Electrical Interconnection As depicted in Figure 22-1, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWI devices output a zero.
22.3.3 Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed. When a Slave recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL (ACK) cycle.
22.3.5 Combining Address and Data Packets into a Transmission A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement handshaking between the Master and the Slave. The Slave can extend the SCL low period by pulling the SCL line low.
Figure 22-7. SCL Synchronization Between Multiple Masters TAhigh TAlow SCL from Master A SCL from Master B SCL Bus Line TBlow Masters Start Counting Low Period TBhigh Masters Start Counting High Period Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line does not match the value the Master had output, it has lost the arbitration.
22.5 Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 22-9. All registers drawn in a thick line are accessible through the AVR data bus. Figure 22-9.
● ● Note: TWBR = Value of the TWI bit rate register. PrescalerValue = Value of the prescaler, see Table 22-8 on page 208. Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load. See Table 29-8 on page 275 for value of pull-up resistor. 22.5.3 Bus Interface Unit This unit contains the data and address shift register (TWDR), a START/STOP controller and arbitration detection hardware.
Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer.
5. The application software should now examine the value of TWSR, to make sure that the address packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load a data packet into TWDR.
Table 22-2. Assembly Code Examples 1 2 Assembly Code Example ldi r16, (1<
22.7 Transmission Modes The TWI can operate in one of four major modes. These are named master transmitter (MT), master receiver (MR), slave transmitter (ST) and slave receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used.
A START condition is sent by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value 1 X 1 0 X 1 0 X TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT flag. The TWI will then test the 2-wire serial bus and generate a START condition as soon as the bus becomes free.
Table 22-3.
Figure 22-12.
22.7.2 Master Receiver Mode In the master receiver mode, a number of data bytes are received from a slave transmitter (slave see Figure 22-13). In order to enter a master mode, a START condition must be transmitted. The format of the following address packet determines whether master transmitter or master receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered.
Table 22-4.
Figure 22-14.
To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device’s Own Slave Address value The upper 7 bits are the address to which the 2-wire serial interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
Table 22-5.
Figure 22-16. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
22.7.4 Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 22-17). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 22-17. Data Transfer in Slave Transmitter Mode VCC Device 1 Device 2 Slave Transmitter Master Receiver Device 3 ........
Table 22-6.
Figure 22-18. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A DATA A $A8 Arbitration lost as master and addressed as slave DATA $B8 A P or S $C0 A $B0 Last data byte transmitted.
22.7.6 Combining Several TWI Modes In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer must be initiated. 2. The EEPROM must be instructed what location should be read. 3. The reading must be performed. 4. The transfer must be finished. Note that data is transmitted both from master to slave and vice versa.
● Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters trying to output a one on SDA while another master outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to slave mode to check if they are being addressed by the winning master. If addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit.
• Bit 7 – TWINT: TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine.
22.9.3 TWSR – TWI Status Register Bit 7 6 5 4 3 2 1 0 (0xB9) TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 Read/Write R R R R R R R/W R/W Initial Value 1 1 1 1 1 0 0 0 TWSR • Bits 7:3 – TWS: TWI Status These 5 bits reflect the status of the TWI logic and the 2-wire serial bus. The different status codes are described later in this section. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value.
22.9.5 TWAR – TWI (Slave) Address Register Bit 7 6 5 4 3 2 1 0 (0xBA) TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 0 TWAR The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the master modes.
23. Analog Comparator 23.1 Overview The analog comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the analog comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the analog comparator.
23.3 Register Description 23.3.1 ADCSRB – ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 (0x7B) – ACME – – – ADTS2 ADTS1 ADTS0 Read/Write R R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bit 6 – ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the analog comparator.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the analog comparator interrupt. The different settings are shown in Table 23-2. Table 23-2.
24. Analog-to-Digital Converter 24.1 Features ● ● ● ● ● ● ● ● ● ● ● ● ● ● 24.2 10-bit resolution 0.5 LSB integral non-linearity ±2 LSB absolute accuracy 13 to 260µs conversion time Up to 76.9kSPS (up to 15kSPS at maximum resolution) 6 multiplexed single ended input channels 2 additional multiplexed single ended input channels Temperature sensor input channel Optional left adjustment for ADC result readout 0 to VCC ADC input voltage range Selectable 1.
Figure 24-1. Analog to Digital Converter Block Schematic Operation ADC Conversion Complete IRQ ADC[9:0] ADPS0 ADPS1 ADPS2 Conversion Logic Sample and Hold Comparator 10-Bit DAC AREF 0 ADC Data Register (ADCH/ADCL) Prescaler Channel Selection Internal 1.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost.
24.4 Prescaling and Conversion Timing Figure 24-3. ADC Prescaler ADEN START Reset 7-Bit ADC Prescaler CK/64 CK/128 CK/32 CK/16 CK/8 CK/4 CK/2 CK ADPS0 ADPS1 ADPS2 ADC Clock Source By default, the successive approximation circuitry requires an input clock frequency between 50kHz and 200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate.
Figure 24-4. ADC Timing Diagram, First Conversion (Single Conversion Mode) Next Conversion First Conversion Cycle Number 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 ADC Clock ADEN ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result MUX and REFS Update Conversion Complete Sample and Hold MUX and REFS Update Figure 24-5.
Figure 24-6. ADC Timing Diagram, Auto Triggered Conversion Next Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample and Hold Prescaler Reset Prescaler Reset Conversion Complete MUX and REFS Update Figure 24-7.
24.5 Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC.
24.6 ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC noise reduction and Idle mode. To make use of this feature, the following procedure should be used: a. Make sure that the ADC is enabled and is not busy converting. Single conversion mode must be selected and the ADC conversion complete interrupt must be enabled. b.
24.6.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. b.
24.6.3 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: ● Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 24-10.
● Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 24-12. Integral Non-linearity (INL) INL Output Code Ideal ADC Actual ADC VREF Input Voltage ● Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 24-13.
24.7 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC result registers (ADCL, ADCH). For single ended conversion, the result is V IN 1024 ADC = --------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 24-3 on page 225 and Table 24-4 on page 226). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB. 24.
24.9 Register Description 24.9.1 ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 (0x7C) REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADMUX • Bit 7:6 – REFS[1:0]: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 24-3.
Table 24-4. Input Channel Selections Note: 1. MUX3...0 Single Ended Input 0000 ADC0 0001 ADC1 0010 ADC2 0011 ADC3 0100 ADC4 0101 ADC5 0110 ADC6 0111 ADC7 1000 ADC8(1) 1001 (reserved) 1010 (reserved) 1011 (reserved) 1100 (reserved) 1101 (reserved) 1110 1.1V (VBG) 1111 For Temperature Sensor. 0V (GND) 24.9.
• Bit 3 – ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC conversion complete interrupt is activated. • Bits 2:0 – ADPS[2:0]: ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC. Table 24-5. ADC Prescaler Selections ADPS2 ADPS1 ADPS0 Division Factor 0 0 0 2 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 24.9.
24.9.4 ADCSRB – ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 (0x7B) – ACME – – – ADTS2 ADTS1 ADTS0 Read/Write R R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bit 7, 5:3 – Reserved These bits are reserved for future use. To ensure compatibility with future devices, these bits must be written to zero when ADCSRB is written.
25. debugWIRE On-chip Debug System 25.1 Features ● ● ● ● ● ● ● ● ● ● 25.
25.4 Software Break Points debugWIRE supports program memory break points by the AVR break instruction. Setting a break point in AVR Studio® will insert a BREAK instruction in the program memory. The instruction replaced by the BREAK instruction will be stored. When program execution is continued, the stored instruction will be executed before continuing from the program memory. A break can be inserted manually by putting the BREAK instruction in the program.
26. Self-Programming the Flash, Atmel ATmega48PA 26.1 Overview In Atmel® ATmega48PA there is no read-while-write support, and no separate boot loader section. The SPM instruction can be executed from the entire flash. The device provides a self-programming mechanism for downloading and uploading program code by the MCU itself. The self-programming can use any available data interface and associated protocol to read code and write (program) that code into the program memory.
26.2 Addressing the Flash During Self-programming The Z-pointer is used to address the SPM commands. Bit 15 14 13 12 11 10 9 8 ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 7 6 5 4 3 2 1 0 Since the flash is organized in pages (see Table 28-9 on page 255), the program counter can be treated as having two different sections.
26.2.2 Reading the Fuse and Lock Bits from Software It is possible to read both the fuse and lock bits from software. To read the Lock bits, load the Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register.
26.2.4 Programming Time for Flash when Using SPM The calibrated RC oscillator is used to time flash accesses. Table 27-6 shows the typical programming time for flash accesses from the CPU. Table 26-1. SPM Programming Time(1) Symbol Min. Programming Time Flash write (page erase, page write, and write lock 3.7ms bits by SPM) Note: 1. Minimum and maximum programming time is per individual operation. Max Programming Time 4.5ms 26.2.
; re-enable the RWW section ldi spmcrval, (1<
26.3 Register Description 26.3.1 SPMCSR – Store Program Memory Control and Status Register The store program memory control and status register contains the control bits needed to control the program memory operations.
27. Boot Loader Support – Read-While-Write Self-Programming The boot loader support applies to Atmel® ATmega48PA/88PA/168PA 27.1 Features ● ● ● ● ● ● ● Note: 27.2 Read-while-write self-programming Flexible boot memory size High security (separate boot lock bits for a flexible protection) Separate fuse to select reset vector Optimized page(1) size Code efficient algorithm Efficient read-modify-write support 1.
27.4 Read-while-write and No Read-while-write Flash Sections Whether the CPU supports read-while-write or if the CPU is halted during a boot loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the flash is also divided into two fixed sections, the read-while-write (RWW) section and the no read-whilewrite (NRWW) section.
Figure 27-1. Read-While-Write versus No Read-While-Write Read While Write (RWW) Section Z-pointer Addresses NRWW Section Z-pointer Addresses RWW Section No Read While Write (NRWW) Section CPU is Halted During the Operation Code located in NRWW Section can be Read During the Operation Figure 27-2.
27.5 Boot Loader Lock Bits If no boot loader capability is needed, the entire flash is available for application code. The boot loader has two separate sets of boot lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. The user can select: ● To protect the entire flash from a software update by the MCU. ● ● ● To protect only the boot loader flash section from a software update by the MCU.
Table 27-4. Boot Reset Fuse(1) BOOTRST Reset Address 1 0 1. Note: 27.7 Reset vector = Application reset (address 0x0000) Reset vector = Boot loader reset (see Table 27-7 on page 247) “1” means unprogrammed, “0” means programmed Addressing the Flash during Self-programming The Z-pointer is used to address the SPM commands.
27.8 Self-Programming the Flash The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
27.8.5 Consideration While Updating BLS Special care must be taken if the user allows the Boot Loader section to be updated by leaving boot lock bit11 unprogrammed. An accidental write to the boot loader itself can corrupt the entire boot loader, and further software updates might be impossible. If it is not necessary to change the boot loader software itself, it is recommended to program the boot lock bit11 to protect the boot loader software from any internal software changes. 27.8.
Similarly, when reading the fuse high byte, load 0x0003 in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the fuse high byte (FHB) will be loaded in the destination register as shown below. Refer to Table 28-6 on page 253 for detailed description and mapping of the fuse high byte.
3. Keep the AVR core in power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR register and thus the flash from unintentional writes. 27.8.12 Programming Time for Flash when Using SPM The calibrated RC oscillator is used to time flash accesses. Table 27-6 shows the typical programming time for flash accesses from the CPU. Table 27-6. SPM Programming Time(1) Symbol Min.
; ldi call ; ldi ldi subi sbci Rdloop: lpm ld cpse jmp sbiw brne read back and check, optional looplo, low(PAGESIZEB) ;init loop variable loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256 YL, low(PAGESIZEB) ;restore pointer YH, high(PAGESIZEB) ; ; Return: in sbrs ready yet ret ; ldi call rjmp return to RWW section verify that RWW section is safe to read Do_spm: ; Wait_spm: in sbrc rjmp ; ; in cli ; Wait_ee: sbic rjmp ; out spm ; out ret 246 re-enable the RWW section spmcrval, (1<
27.8.14 Atmel ATmega88PA Boot Loader Parameters In Table 27-7 through Table 27-9, the parameters used in the description of the self programming are given. Table 27-7.
27.8.15 Atmel ATmega168PA Boot Loader Parameters In Table 27-10 through Table 27-12, the parameters used in the description of the self programming are given. Table 27-10.
27.9 Register Description 27.9.1 SPMCSR – Store Program Memory Control and Status Register The store program memory control and status register contains the control bits needed to control the boot loader operations.
• Bit 0 – SELFPRGEN: Self Programming Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLBSET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SELFPRGEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored.
28. Memory Programming 28.1 Program And Data Memory Lock Bits The Atmel® ATmega48PA provides two lock bits and the Atmel ATmega48PA/88PA/168PA provides six lock bits. These can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 28-2. The lock bits can only be erased to “1” with the chip erase command.
Table 28-3. Lock Bit Protection Modes(1)(2) (only Atmel ATmega48PA/88PA/168PA) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the application section. 2 1 0 SPM is not allowed to write to the application section. 3 0 0 SPM is not allowed to write to the application section, and LPM executing from the boot loader section is not allowed to read from the application section.
Table 28-5. Extended Fuse Byte for Atmel ATmega88PA/168PA Extended Fuse Byte Bit No Description Default Value – 7 – 1 – 6 – 1 – 5 – 1 – 4 – 1 – 3 – 1 BOOTSZ1 2 Select boot size (see Table 27-7 on page 247 and Table 27-10 on page 248 for details) 0 (programmed)(1) BOOTSZ0 1 Select boot size (see Table 27-7 on page 247 and Table 27-10 on page 248 for details) 0 (programmed)(1) Note: BOOTRST 0 Select reset vector 1 (unprogrammed) 1.
Table 28-7. Fuse Low Byte Low Fuse Byte Bit No Description Default Value (4) 7 Divide clock by 8 0 (programmed) (3) CKOUT 6 Clock output 1 (unprogrammed) SUT1 5 Select start-up time 1 (unprogrammed)(1) SUT0 4 Select start-up time 0 (programmed)(1) CKSEL3 3 Select clock source 0 (programmed)(2) CKSEL2 2 Select clock source 0 (programmed)(2) CKSEL1 1 Select clock source 1 (unprogrammed)(2) CKDIV8 Note: CKSEL0 0 Select clock source 0 (programmed)(2) 1.
28.5 Page Size Table 28-9. No. of Words in a Page and No. of Pages in the Flash Device Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB Atmel ATmega48PA/ 88PA/168PA 2K words (4K bytes) 32 words PC[4:0] 64 PC[10:5] 10 Atmel ATmega88PA 4K words (8K bytes) 32 words PC[4:0] 128 PC[11:5] 11 Atmel ATmega168PA 8K words (16K bytes) 64 words PC[5:0] 128 PC[12:6] 12 Table 28-10. No. of Words in a Page and No. of Pages in the EEPROM EEPROM Size Page Size PCWORD No.
Table 28-11.
28.7 Parallel Programming 28.7.1 Enter Programming Mode The following algorithm puts the device in parallel (high-voltage) programming mode: 1. Set Prog_enable pins listed in Table 28-12 on page 256 to “0000”, RESET pin to 0V and VCC to 0V. 2. Apply 4.5 - 5.5V between VCC and GND. Ensure that VCC reaches at least 1.8V within the next 20µs. 3. Wait 20 - 60µs, and apply 11.5 - 12.5V to RESET. 4.
28.7.4 Programming the Flash The Flash is organized in pages, see Table 28-9 on page 255. When programming the flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for write flash. 4.
Figure 28-2. Addressing the Flash Which is Organized in Pages(1) PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN PAGE Program Memory Page Page Instruction Word PCWORD [PAGEMSB : 0] 00 01 02 PAGEEND Note: 1. PCPAGE and PCWORD are listed in Table 28-9 on page 255. Figure 28-3. Programming the Flash Waveforms(1) F DATA A B C D E B C D E G 0x10 ADDR. LOW DATA LOW DATA HIGH XX ADDR. LOW DATA LOW DATA HIGH XX ADDR.
28.7.5 Programming the EEPROM The EEPROM is organized in pages, see Table 28-10 on page 255. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to Section 28.7.4 “Programming the Flash” on page 258 for details on command, address and data loading): 1. A: Load command “0001 0001”. 2. G: Load address high byte (0x00 - 0xFF). 3.
28.7.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to Section 28.7.4 “Programming the Flash” on page 258 for details on command and address loading): 1. A: Load command “0000 0011”. 2. G: Load address high byte (0x00 - 0xFF). 3. B: Load address low byte (0x00 - 0xFF). 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”. 28.7.
Figure 28-5. Programming the FUSES Waveforms Write Fuse Low byte DATA A C 0x40 DATA XX Write Fuse High byte A C 0x40 DATA XX Write Extended Fuse byte A C 0x40 DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE 28.7.11 Programming the Lock Bits The algorithm for programming the lock bits is as follows (refer to Section 28.7.4 “Programming the Flash” on page 258 for details on command and data loading): 1. A: Load command “0010 0000”. 2. C: Load data low byte.
Figure 28-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read Fuse Low Byte 0 0 Extended Fuse Byte 1 DATA BS2 Lock Bits 0 1 BS1 Fuse High Byte 1 BS2 28.7.13 Reading the Signature Bytes The algorithm for reading the signature bytes is as follows (refer to Section 28.7.4 “Programming the Flash” on page 258 for details on command and address loading): 1. A: Load command “0000 1000”. 2. B: Load address low byte (0x00 - 0x02). 3. Set OE to “0”, and BS1 to “0”.
28.8 Serial Downloading Both the flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the programming enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 28-15 on page 264, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface.
28.8.2 Serial Programming Algorithm When writing serial data to the Atmel® ATmega48PA/88PA/168PA, data is clocked on the rising edge of SCK. When reading data from the Atmel ATmega48PA/88PA/168PA, data is clocked on the falling edge of SCK. See Figure 28-9 for timing details. To program and verify the Atmel ATmega48PA/88PA/168PA in the serial programming mode, the following sequence is recommended (see serial programming instruction set in Table 28-17 on page 266): 1.
28.8.3 Serial Programming Instruction set Table 28-17 on page 266 and Figure 28-8 on page 267 describes the Instruction set. Table 28-17.
If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’ before the next instruction is carried out. Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 28-8. Figure 28-8.
29. Electrical Characteristics All AC/DC characteristics contained in this datasheet are based on characterization of the Atmel® ATmega48PA/88PA/168PA AVR microcontroller manufactured in an automotive process technology. 29.1 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
29.2 DC Characteristics Table 29-1. Common DC Characteristics TA = -40°C to 125°C, VCC = 2.7V to 5.5V (Unless Otherwise Noted) Parameter Condition Input low voltage, except XTAL1 and RESET pin Symbol Min. VCC = 2.7V - 5.5V VIL Input high voltage, except XTAL1 and RESET pins VCC = 2.4V - 5.5V Input low voltage, XTAL1 pin Max. Unit –0.3 0.3VCC(1) V VIH 0.6VCC(2) VCC + 0.5 V VCC = 2.7V - 5.5V VIL1 –0.3 0.1VCC(1) V Input high voltage, XTAL1 pin VCC = 2.4V - 5.5V VIH1 0.
29.2.1 DC Characteristics Table 29-2. DC Characteristics - TA = –40°C to +125°C, VCC = 2.7V to 5.5V (Unless Otherwise Noted) Parameter Power Supply Current(1) Typ.(2) Max. Unit Active 4MHz, VCC = 3V 1.3 2.4 mA Active 8MHz, VCC = 5V 4.6 10 mA Active 16MHz, VCC = 5V 8.4 16 mA Idle 4MHz, VCC = 3V 0.2 0.6 mA 0.9 1.6 mA Condition Symbol Idle 8MHz, VCC = 5V ICC Idle 16MHz, VCC = 5V 1.8 4 mA WDT enabled, VCC = 3V 4.2 44 µA WDT enabled, VCC = 5V 6.
29.4 Clock Characteristics 29.4.1 Calibrated Internal RC Oscillator Accuracy Table 29-3. Calibration Accuracy of Internal RC Oscillator Frequency Default 3V Factory Calibration 8.0MHz 5V Factory Calibration 8.0MHz Watchdog Oscillator 128kHz VCC Temperature Calibration Accuracy 3V 25°C ±1% 2.7V to 5.5V –40°C to 125°C ±14% 5V 25°C ±1% 4.5V to 5.5V –40°C to 125°C ±10% 2.7V to 5.5V –40°C to 125°C ±40% 29.4.2 External Clock Drive Waveforms Figure 29-2.
29.5 System and Reset Characteristics Table 29-5. Power on Reset Specifications(1) Parameter Symbol Power-on reset threshold voltage (rising) Min. VPOT (2) Power-on reset threshold voltage (falling) Vpormax VCC Min. start voltage to ensure internal power-on reset signal Vpormin VCC rise rate to ensure power-on reset 0.6 VCCRR 0.01 VRST 0.2Vcc Minimum pulse width on RESET pin tRST 2.5 Bandgap reference voltage VBG 1.0 Brown-out detector hysteresis Notes: 1. Values are guidelines only.
29.6 SPI Timing Characteristics See Figure 29-3 and Figure 29-4 for details. Table 29-7. SPI Timing Parameters No. Description Mode 1 SCK period Master See Table 19-5 2 SCK high/low Master 50% duty cycle 3 Rise/fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
Figure 29-3. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 ... MSB LSB 8 7 MOSI (Data Output) ... MSB LSB Figure 29-4. SPI Interface Timing Requirements (Slave Mode) SS 16 10 9 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 ... MSB LSB 17 15 MISO (Data Output) 274 MSB ATmega48PA/88PA/168PA [DATASHEET] 9223F–AVR–04/14 ...
29.7 Two-wire Serial Interface Characteristics Table 29-8 describes the requirements for devices connected to the 2-wire serial bus. The Atmel® ATmega48PA/88PA/168PA 2-wire serial interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 29-5. Table 29-8. Two-wire Serial Bus Requirements Parameter Condition Symbol Min. Max Unit Input low-voltage VIL -0.3 0.3 VCC V Input high-voltage VIH 0.7 VCC VCC + 0.5 V – V 0.
Figure 29-5. Two-wire Serial Bus Timing tOF tHIGH tLOW tR tLOW SCL tSU;STA tHD;DAT tHD;STA tSU;STO tSU;DAT SDA tBUF 29.8 ADC Characteristics Table 29-9. ADC Characteristics Parameter Condition Resolution –40°C to 125°C, 2.70V to 5.50V ADC clock = 200kHz Symbol Absolute accuracy VCC = 4V, VREF = 4V TUE 2.2 3.5 LSB Integral non-linearity VCC = 4V, VREF = 4V INL 0.6 1.5 LSB Differential non-linearity VCC = 4V, VREF = 4V DNL 0.3 0.7 LSB Gain error VCC = 4V, VREF = 4V –4.
29.9 Parallel Programming Characteristics Table 29-10. Parallel Programming Characteristics, VCC = 5V ±10% Parameter Symbol Programming enable voltage Min. VPP Programming enable current Typ 11.5 IPP Max Unit 12.
Figure 29-7. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) Load Address (Low Byte) Load Data (Low Byte) Load Data (High Byte) tXLXH Load Address (Low Byte) Load Data tPLXH tXLPH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 29-6 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 29-8.
30. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A square wave generator with rail-to-rail output is used as clock source. 30.1 ATmega48PA Typical Characteristics 30.1.1 Active Supply Current Figure 30-1. Active Supply Current versus Low Frequency (0.1-1.0MHz) 1.4 6.0 5. 5 1.2 ICC (mA) 5. 0 1.0 4.
30.1.2 Idle Supply Current Figure 30-3. Idle Supply Current versus Low Frequency (0.1-1.0MHz) 0.18 0.16 6.0 0.14 5.5 5.0 ICC (mA) 0.12 4.5 0.1 4.0 0.08 3.6 3.3 0.06 3.0 0.04 2.7 0.02 2.5 2.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2.0 1.8 Frequency (MHz) 1.62 Figure 30-4. Idle Supply Current versus Frequency (1-16MHz) 4.0 3.5 6.0 5.5 3.0 ICC (mA) 5.0 2.5 4.5 2.0 4.0 3.6 1.5 3.3 1.0 3.0 2.7 0.5 2.5 2.2 0 0 2 4 6 8 10 12 Frequency (MHz) 14 16 18 20 2.
30.1.3 Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in active and idle mode. The enabling or disabling of the I/O modules are controlled by the power reduction register. See Section 10.9 “Power Reduction Register” on page 37 for details. Table 30-1.
30.1.4 Power-down Supply Current Figure 30-5. Power-down Supply Current versus VCC (Watchdog Timer Disabled) 60 50 ICC (µA) 40 150 30 125 85 20 25 -40 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) Figure 30-6. Power-down Supply Current versus VCC (Watchdog Timer Enabled) 100 90 80 ICC (µA) 70 60 150 50 125 40 85 30 25 20 -40 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) 30.1.5 Pin Pull-up Figure 30-7. I/O Pin Pull-up Resistor Current versus Input Voltage (VCC = 5.
Figure 30-8. Reset Pull-up Resistor Current versus Reset Pin Voltage (VCC = 5V) 140 120 IRESET (µA) 100 80 150 125 60 85 40 25 20 -40 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -20 VRESET (V) 30.1.6 Pin Driver Strength Figure 30-9. I/O Pin Output Voltage versus Sink Current (VCC = 3V) 0.3 0.25 VOL (V) 0.2 150 0.15 125 85 0.1 25 -40 0.05 0 0 1 2 3 4 5 IOL (mA) Figure 30-10. I/O Pin Output Voltage versus Sink Current (VCC = 5V) 0.8 0.7 VOL (V) 0.6 0.5 0.4 150 0.3 125 85 0.
Figure 30-11. I/O Pin Output Voltage versus Source Current (VCC = 3V) 3.1 3.0 2.9 VOH (V) 2.8 2.7 150 2.6 125 2.5 85 25 2.4 -40 2.3 2.2 0 1 2 3 4 5 6 7 8 9 10 IOH (mA) Figure 30-12. I/O Pin Output Voltage versus Source Current (VCC = 5V) 5.2 5 VOH (V) 4.8 4.6 150 4.4 125 4.2 85 25 4 -40 3.8 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) 30.1.7 Pin Threshold and Hysteresis Figure 30-13. I/O Pin Input Threshold Voltage versus VCC (VIH, I/O Pin read as ‘1’) 4 3.
Figure 30-14. I/O Pin Input Threshold Voltage versus VCC (VIL, I/O Pin read as ‘0’) 2.5 Threshold (V) 2 150 125 1.5 85 25 1 -40 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-15. Reset Input Threshold Voltage versus VCC (VIH, I/O Pin read as ‘1’) 5 4.5 Threshold (V) 4 3.5 3 150 2.5 125 2 85 1.5 25 1 -40 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-16. Reset Input Threshold Voltage versus VCC (VIL, I/O Pin read as ‘0’) 2.5 2 Threshold (V) 150 125 1.
30.1.8 BOD Threshold Figure 30-17. BOD Thresholds versus Temperature (BODLEVEL is 1.8V) 2 1.95 Threshold (V) 1.9 1.85 1.8 1 0 1.75 1.7 1.65 1.6 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 Temperature (°C) Figure 30-18. BOD Thresholds versus Temperature (BODLEVEL is 2.7V) 2.9 2.85 Threshold (V) 2.8 2.75 2.7 1 2.65 0 2.6 2.55 2.5 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 Temperature (°C) Figure 30-19.
Figure 30-20. Bandgap Voltage versus VCC 1.15 Bandgap Voltage (V) 1.125 150 1.1 125 1.075 85 1.05 25 1.025 -40 1 0.975 0.95 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.1.9 Internal Oscillator Speed Figure 30-21. Watchdog Oscillator Frequency versus Temperature 150 6.0 5.5 140 5.0 FRC (kHz) 4.5 130 4.0 3.6 3.3 120 3.0 2.7 110 2.4 2.2 100 2.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (°C) 1.8 1.6 Figure 30-22.
Figure 30-23. Calibrated 8MHz RC Oscillator Frequency versus VCC 8.4 8.3 8.2 FRC (MHz) 150 8.1 125 85 8 25 7.9 -40 7.8 7.7 7.6 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VCC (V) Figure 30-24. Calibrated 8MHz RC Oscillator Frequency versus Temperature 8.4 6.0 8.3 5.5 FRC (MHz) 8.2 5.0 4.5 8.1 4.0 3.6 8.0 3.3 7.9 3.0 2.7 7.8 2.5 7.7 2.2 7.6 2.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 1.8 Temperature (°C) Figure 30-25.
30.1.10 Reset Pulse width Figure 30-26. Minimum Reset Pulse width versus VCC 2500 Pulse width (ns) 2000 1500 150 1000 125 85 25 500 -40 0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8 VCC (V) 30.2 ATmega88PA Typical Characteristics 30.2.1 Active Supply Current Figure 30-27. Active Supply Current versus Low Frequency (0.1-1.0MHz) 1.4 6.0 5. 5 1.2 ICC (mA) 5. 0 1.0 4. 5 0.8 3. 6 4.0 3. 3 0.6 3.0 2. 7 0.4 2. 4 0.2 2. 1 0 1. 8 2.0 0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency (MHz) 0.
Figure 30-28. Active Supply Current versus Frequency (1-16MHz) 20 18 6.0 16 5.5 5.0 ICC (mA) 14 4.5 12 4.0 10 3.6 8 3.3 6 3.0 4 2.7 2 2.5 2.2 0 0 2 4 6 8 10 12 14 16 18 20 2.0 1.8 Frequency (MHz) 30.2.2 Idle Supply Current Figure 30-29. Idle Supply Current versus Low Frequency (0.1-1.0MHz) 0.18 0.16 6.0 0.14 5.5 5.0 ICC (mA) 0.12 4.5 0.1 4.0 0.08 3.6 3.3 0.06 3.0 0.04 2.7 0.02 2.5 2.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2.0 1.
30.2.3 Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in active and idle mode. The enabling or disabling of the I/O modules are controlled by the power reduction register. See Section 10.9 “Power Reduction Register” on page 37 for details. Table 30-3.
30.2.4 Power-down Supply Current Figure 30-31. Power-down Supply Current versus VCC (Watchdog Timer Disabled) 60 50 ICC (µA) 40 150 30 125 85 20 25 -40 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) Figure 30-32. Power-down Supply Current versus VCC (Watchdog Timer Enabled) 100 90 80 ICC (µA) 70 60 150 50 125 40 85 30 25 20 -40 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) 30.2.5 Pin Pull-up Figure 30-33. I/O Pin Pull-up Resistor Current versus Input Voltage (VCC = 5.
Figure 30-34. Reset Pull-up Resistor Current versus Reset Pin Voltage (VCC = 5V) 140 120 IRESET (µA) 100 80 150 125 60 85 40 25 -40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET (V) 30.2.6 Pin Driver Strength Figure 30-35. I/O Pin Output Voltage versus Sink Current (VCC = 3V) 0.3 0.25 VOL (V) 0.2 150 0.15 125 85 0.1 25 -40 0.05 0 0 1 2 3 4 5 IOL (mA) Figure 30-36. I/O Pin Output Voltage versus Sink Current (VCC = 5V) 0.8 0.7 VOL (V) 0.6 150 0.5 125 0.4 85 25 0.
Figure 30-37. I/O Pin Output Voltage versus Source Current (VCC = 3V) 3.1 3.0 2.9 VOH (V) 2.8 2.7 150 2.6 125 2.5 85 25 2.4 -40 2.3 2.2 0 1 2 3 4 5 6 7 8 9 10 IOH (mA) Figure 30-38. I/O Pin Output Voltage versus Source Current (VCC = 5V) 5.2 5 VOH (V) 4.8 4.6 150 4.4 125 4.2 85 25 4 -40 3.8 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) 30.2.7 Pin Threshold and Hysteresis Figure 30-39. I/O Pin Input Threshold Voltage versus VCC (VIH, I/O Pin read as ‘1’) 4 3.
Figure 30-40. I/O Pin Input Threshold Voltage versus VCC (VIL, I/O Pin read as ‘0’) 2.5 Threshold (V) 2 150 125 1.5 85 25 1 -40 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-41. Reset Input Threshold Voltage versus VCC (VIH, I/O Pin read as ‘1’) 5 4.5 Threshold (V) 4 3.5 3 150 2.5 125 2 85 1.5 25 1 -40 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-42. Reset Input Threshold Voltage versus VCC (VIL, I/O Pin read as ‘0’) 2.5 2 Threshold (V) 150 125 1.
30.2.8 BOD Threshold Figure 30-43. BOD Thresholds versus Temperature (BODLEVEL is 1.8V) 2 1.95 Threshold (V) 1.9 1.85 1 1.8 0 1.75 1.7 1.65 1.6 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 Temperature (°C) Figure 30-44. BOD Thresholds versus Temperature (BODLEVEL is 2.7V) 2.9 2.85 Threshold (V) 2.8 2.75 1 2.7 0 2.65 2.6 2.55 2.5 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 Temperature (°C) Figure 30-45.
Figure 30-46. Bandgap Voltage versus VCC 1.1 Bandgap Voltage (V) 1.098 1.096 1.094 150 1.092 125 1.09 85 1.088 25 1.086 -40 1.084 1.082 1.08 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.2.9 Internal Oscillator Speed Figure 30-47. Watchdog Oscillator Frequency versus Temperature 150 6.0 5.5 140 5.0 FRC (kHz) 4.5 130 4.0 3.6 3.3 120 3.0 2.7 110 2.4 2.2 100 2.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 1.8 Temperature (°C) 1.6 Figure 30-48.
Figure 30-49. Calibrated 8MHz RC Oscillator Frequency versus VCC 8.4 8.3 150 FRC (MHz) 8.2 125 8.1 85 8 25 -40 7.9 7.8 7.7 7.6 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VCC (V) Figure 30-50. Calibrated 8MHz RC Oscillator Frequency versus Temperature 8.4 6.0 8.3 5.5 8.2 5.0 FRC (MHz) 4.5 8.1 4.0 3.6 8.0 3.3 7.9 3.0 2.7 7.8 2.5 7.7 2.2 2.0 7.6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 1.8 Temperature (°C) Figure 30-51.
30.2.10 Reset Pulse Width Figure 30-52. Minimum Reset Pulse width versus VCC 1800 1600 Pulse width (ns) 1400 150 1200 125 1000 85 800 25 600 -40 400 200 0 1.8 2.8 3.8 4.8 VCC (V) 30.3 ATmega168PA Typical Characteristics 30.3.1 Active Supply Current Figure 30-53. Active Supply Current versus Low Frequency (0.1-1.0MHz) 1.6 6.0 1.4 5. 5 1.2 ICC (mA) 5. 0 1.0 4. 5 4.0 0.8 3. 6 0.6 3. 3 3.0 0.4 2. 7 0.2 2. 4 0 0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency (MHz) 0.7 0.8 0.
Figure 30-54. Active Supply Current versus Frequency (1-16MHz) 20 6.0 18 5.5 ICC (mA) 16 5.0 14 4.5 12 4.0 10 3.6 3.3 8 3.0 6 2.7 4 2.4 2 2.2 2.0 0 0 2 4 6 8 10 12 14 16 18 20 1.8 Frequency (MHz) 30.3.2 Idle Supply Current Figure 30-55. Idle Supply Current versus Low Frequency (0.1-1.0MHz) 0.2 6.0 0.18 5.5 ICC (mA) 0.16 5.0 0.14 4.5 0.12 4.0 0.1 3.6 3.3 0.08 3.0 0.06 2.7 0.04 2.4 0.02 2.2 2.0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.
30.3.3 Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in active and idle mode. The enabling or disabling of the I/O modules are controlled by the power reduction register. See Section 10.9 “Power Reduction Register” on page 37 for details. Table 30-5.
30.3.4 Power-down Supply Current Figure 30-57. Power-down Supply Current versus VCC (Watchdog Timer Disabled) 50 45 40 ICC (µA) 35 30 150 25 125 20 85 25 15 -40 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-58. Power-down Supply Current versus VCC (Watchdog Timer Enabled) 200 180 160 ICC (µA) 140 120 150 100 125 80 85 60 25 40 -40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.3.5 Pin Pull-up Figure 30-59.
Figure 30-60. Reset Pull-up Resistor Current versus Reset Pin Voltage (VCC = 5V) 120 100 IRESET (µA) 80 60 150 125 40 85 25 20 -40 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -20 VRESET (V) 30.3.6 Pin Driver Strength Figure 30-61. I/O Pin Output Voltage versus Sink Current (VCC = 3V) 0.3 0.25 150 VOL (V) 0.2 125 0.15 85 0.1 -40 25 0.05 0 0 1 2 3 4 5 IOL (mA) Figure 30-62. I/O Pin Output Voltage versus Sink Current (VCC = 5V) 0.8 0.7 VOL (V) 0.6 150 0.5 125 0.4 85 25 0.
Figure 30-63. I/O Pin Output Voltage versus Source Current (VCC = 3V) 3.1 3.0 2.9 VOH (V) 2.8 2.7 150 2.6 125 2.5 85 25 2.4 -40 2.3 2.2 0 1 2 3 4 5 6 7 8 9 10 IOH (mA) Figure 30-64. I/O Pin Output Voltage versus Source Current (VCC = 5V) 5.2 5 VOH (V) 4.8 4.6 150 4.4 125 4.2 85 25 4 -40 3.8 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) 30.3.7 Pin Threshold and Hysteresis Figure 30-65. I/O Pin Input Threshold Voltage versus VCC (VIH, I/O Pin read as ‘1’) 3 Threshold (V) 2.
Figure 30-66. I/O Pin Input Threshold Voltage versus VCC (VIL, I/O Pin read as ‘0’) 2.5 Threshold (V) 2 150 1.5 125 85 1 25 -40 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-67. Reset Input Threshold Voltage versus VCC (VIH, I/O Pin read as ‘1’) 3 Threshold (V) 2.5 2 150 125 1.5 85 1 -40 25 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-68. Reset Input Threshold Voltage versus VCC (VIL, I/O Pin read as ‘0’) 2.5 Threshold (V) 2 1.5 150 125 1 85 25 0.
30.3.8 BOD Threshold Figure 30-69. BOD Thresholds versus Temperature (BODLEVEL is 1.8V) 1.84 Threshold (V) 1.83 1.82 1.81 1 0 1.80 1.79 1.78 1.77 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 Temperature (°C) Figure 30-70. BOD Thresholds versus Temperature (BODLEVEL is 2.7V) 2.78 Threshold (V) 2.76 2.74 2.72 1 0 2.70 2.68 2.66 2.64 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 Temperature (°C) Figure 30-71.
Figure 30-72. Bandgap Voltage versus VCC 1.11 Bandgap Voltage (V) 1.105 1.1 150 125 1.095 85 1.09 -40 25 1.085 1.08 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.3.9 Internal Oscillator Speed Figure 30-73. Watchdog Oscillator Frequency versus Temperature 140 6.0 135 5.5 FRC (kHz) 130 5.0 4.5 125 4.0 120 3.6 3.3 115 3.0 110 2.7 2.4 105 2.2 100 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 2.0 1.8 Temperature (°C) Figure 30-74.
Figure 30-75. Calibrated 8MHz RC Oscillator Frequency versus VCC 8.4 8.3 150 FRC (MHz) 8.2 125 8.1 85 8 25 -40 7.9 7.8 7.7 7.6 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VCC (V) Figure 30-76. Calibrated 8MHz RC Oscillator Frequency versus Temperature 8.4 6.0 8.3 5.5 8.2 5.0 FRC (MHz) 4.5 8.1 4.0 3.6 8.0 3.3 7.9 3.0 2.7 7.8 2.5 7.7 2.2 2.0 7.6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 1.8 Temperature (°C) Figure 30-77.
Reset Pulse Width Figure 30-78. Minimum Reset Pulse width versus VCC 2000 1800 1600 Pulse width (ns) 30.3.10 1400 150 1200 125 1000 85 800 25 600 -40 400 200 0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.
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32. Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clocks ST Z, Rr Store indirect (Z) Rr None 2 ST Z+, Rr Store indirect and post-inc. (Z) Rr, Z Z + 1 None 2 ST -Z, Rr Store indirect and pre-dec.
33. Ordering Information 33.1 ATmega48PA/88PA/168PA Speed (MHz) 16(2) Notes: Power Supply (V) 2.7 - 5.5 Ordering Code Package(1) ATmega48PA-15AZ MA ATmega48PA-15MZ PN ATmega88PA-15AZ MA ATmega88PA-15MZ PN ATmega168PA-15AZ MA Operational Range Automotive (–40°C to 125°C) ATmega168PA-15MZ PN 1. Pb-free packaging complies to the european directive for restriction of hazardous substances (RoHS directive).Also halide free and fully green. 2. See Section 29.3 “Speed Grades” on page 270.
34. Packaging Information 34.1 MA Drawings not scaled A A2 A1 D1 32 1 E1 e L 0°~7° Top View C Side View D COMMON DIMENSIONS (Unit of Measure = mm) Symbol MIN NOM A MAX A1 0.05 A2 0.95 1.00 1.05 D/E 8.75 9.00 9.25 D1/E1 6.90 7.00 7.10 C 0.09 0.20 L 0.45 0.75 b 0.30 0.45 E b Bottom View NOTE 1.20 0.15 e 0.80 TYP. n 32 2 Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026, Variation ABA. 2.
34.2 PN Drawings not scaled A A3 D A1 N 1 0.30 Dia. Typ. Laser Marking E Seating Plane C 0.080 C Top View L Side View D2 COMMON DIMENSIONS b (Unit of Measure = mm) Option A Pin 1# Chamfer (C 0.30) E2 Option B PIN1 ID 1 Pin 1# Notch (C 0.20 R) See Options A, B e Symbol MIN NOM MAX A 0.80 0.85 0.90 A1 A3 0.00 NOTE 0.05 0.20 REF D/E 5.00 BSC D2/E2 3.00 3.10 3.20 L 0.30 0.40 0.50 b 0.18 0.25 0.30 e 0.50 BSC n 32 2 Bottom View Notes: 1.
35. Errata 35.1 Errata ATmega48PA The revision letter in this section refers to the revision of the ATmega48PA/88PA/168PA device. 35.1.1 Rev. D ● 1. Analog MUX can be turned off when setting ACME bit Analog MUX can be turned off when setting ACME bit If the ACME (analog comparator multiplexer enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared. Problem Fix/Workaround Clear the MUX3 bit before setting the ACME bit. 35.
36. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 9223F-AVR-04/14 Put datasheet in the latest templage 9223E-AVR-02/13 Table 28-8 “Device ID” on page 297 updated 9223D-AVR-05/12 Set datasheet from “Preliminary” to “Standard” Features on page 1 updated Figure 25-1 “The debugWIRE Setup” on page 267 updated Section 28.
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