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13. System Clock and Clock Options

14.3 Idle Mode

When the SM[2:0] bits are written to '000', the SLEEP instruction makes the MCU enter Idle mode,

stopping the CPU but allowing the SPI, USART, analog comparator, two-wire serial interface, timer/

counters, watchdog, and the interrupt system to continue operating. This Sleep mode basically halts

clk

CPU

and clk

FLASH

, while allowing the other clocks to run.

The Idle mode enables the MCU to wake-up from external triggered interrupts as well as internal ones

like the timer overflow and USART transmit complete interrupts. If wake-up from the analog comparator

interrupt is not required, the analog comparator can be powered-down by setting the ACD bit in the

Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle

mode.

14.4 ADC Noise Reduction Mode

When the SM[2:0] bits are written to '001', the SLEEP instruction makes the MCU enter ADC Noise

Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the two-wire serial

interface address watch, Timer/Counter

(1)

, and the Watchdog to continue operating (if enabled). This

sleep mode basically halts clk

I/O

, clk

CPU

, and clk

FLASH

, while allowing the other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC

is enabled, a conversion starts automatically when this mode is entered. Apart from the ADC conversion

complete interrupt, only these events can wake-up the MCU from ADC Noise Reduction mode:

• External Reset

• Watchdog System Reset

• Watchdog Interrupt

• Brown-out Reset

• Two-wire Serial Interface Address Match

• Timer/Counter Interrupt

• SPM/EEPROM Ready Interrupt

• External Level Interrupt on INT

• Pin Change Interrupt

Note: 1. Timer/Counter will only keep running in Asynchronous mode.