Datasheet

18.4.1 MCU Control Register
Name: MCUCR
Offset: 0x55
Reset: 0x00
Property: When addressing as I/O register: address offset is 0x35
The MCU Control register controls the placement of the interrupt vector table in order to move interrupts
between application and boot space. (For ATmega88A and ATmega168A )
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Bit 7 6 5 4 3 2 1 0
PUD IVSEL IVCE
Access
R/W R/W R/W
Reset 0 0 0
Bit 4 – PUD Pull-up Disable
When this bit is written to one, the pull ups in the I/O ports are disabled even if the DDxn and PORTxn
registers are configured to enable the pull ups ({DDxn, PORTxn} = 0b01).
Bit 1 – IVSEL Interrupt Vector Select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Flash memory.
When this bit is set (one), the interrupt vectors are moved to the beginning of the boot loader section of
the Flash. The actual address of the start of the boot Flash section is determined by the BOOTSZ fuses.
To avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to
change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the
same cycle as IVCE is written, and interrupts remain disabled until after the instruction following the write
to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status register
is unaffected by the automatic disabling.
Note: If interrupt vectors are placed in the boot loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the application section. If interrupt vectors are placed in the
application section and Boot Lock bit BLB12 is programmed, interrupts are disabled while executing from
the boot loader section.
Bit 0 – IVCE Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware
four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as
explained in the IVSEL description above. See the code example below.
Assembly Code Example
Move_interrupts:
; Get MCUCR
ATmega48A/88A/168A
I/O-Ports
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002007A-page 124