Datasheet

17.1.4. EIFR – External Interrupt Flag Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: EIFR
Offset: 0x38
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x58
Bit 7 6 5 4 3 2 1 0
INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 INTF0
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – INTFn: External Interrupt Flags n [n = 7:0]
When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes set
(one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7:0 in EIMSK, are set (one), the
MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. These flags are always cleared when
INT7:0 are configured as level interrupt. Note that when entering sleep mode with the INT3:0 interrupts
disabled, the input buffers on these pins will be disabled. This may cause a logic change in internal
signals which will set the INTF3:0 flags. Refer to Digital Input Enable and Sleep Modes on page 96 for
more information.
Atmel ATmega64A [DATASHEET]
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