Datasheet

17.1.3. EIMSK – External Interrupt Mask Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: EIMSK
Offset: 0x39
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x59
Bit 7 6 5 4 3 2 1 0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – INTn: External Interrupt Request n Enable [n = 7:0]
When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the
corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt
Control Registers – EICRA and EICRB – defines whether the external interrupt is activated on rising or
falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is
enabled as an output. This provides a way of generating a software interrupt.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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