Datasheet

17.1.2. EICRB – External Interrupt Control Register B
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
This Register can not be reached in ATmega103 compatibility mode, but the initial value defines INT3:0
as low level interrupts, as in ATmega103.
Name: EICRB
Offset: 0x3A
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x5A
Bit 7 6 5 4 3 2 1 0
ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:6 – ISC7n: External Interrupt 7 Sense Control Bits [n = 1:0]
The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate
the interrupts are defined in table Interrupt Sense Control below. The value on the INT7:4 pins are
sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one
clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled.
If low level interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request
as long as the pin is held low.
Table 17-3 Interrupt Sense Control
(1)
ISCn1 ISCn0 Description
0 0 The low level of INTn generates an interrupt request.
0 1 Reserved.
1 0 The falling edge of INTn generates an interrupt request.
1 1 The rising edge of INTn generates an interrupt request.
Note: 1. n = 7, 6, 5 or 4. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by
clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are
changed.
Bits 5:4 – ISC6n: External Interrupt 6 Sense Control Bits [n = 1:0]
Refer to ISC7n bit description above.
Bits 3:2 – ISC5n: External Interrupt 5 Sense Control Bits [n = 1:0]
Refer to ISC7n bit description above.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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