Datasheet

17.1.1. EICRA – External Interrupt Control Register A
This Register can not be reached in ATmega103 compatibility mode, but the initial value defines INT3:0
as low level interrupts, as in ATmega103.
Name: EICRA
Offset: 0x6A
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:6 – ISC3n: External Interrupt 3 Sense Control Bits [n = 1:0]
The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate
the interrupts are defined in table Interrupt Sense Control below. Edges on INT3:INT0 are registered
asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width given in table Asynchronous
External Interrupt Characteristics below will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of
the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will
generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can
occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK
Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing
a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled.
Table 17-1 Interrupt Sense Control
(1)
ISCn1 ISCn0 Description
0 0 The low level of INTn generates an interrupt request.
0 1 Reserved.
1 0 The falling edge of INTn generates asynchronously an interrupt request.
1 1 The rising edge of INTn generates asynchronously an interrupt request.
Note: 1. n = 3, 2, 1 or 0. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by
clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are
changed.
Table 17-2 Asynchronous External Interrupt Characteristics
Symbol Parameter Condition Min Typ Max Units
t
INT
Minimum pulse width for
asynchronous external interrupt
50 ns
Bits 5:4 – ISC2n: External Interrupt 2 Sense Control Bits [n = 1:0]
Refer to ISC3n bit description above.
Atmel ATmega64A [DATASHEET]
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