Datasheet

16.2.1. MCUCR – MCU Control Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: MCUCR
Offset: 0x35
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x55
Bit 7 6 5 4 3 2 1 0
IVSEL IVCE
Access
R/W R/W
Reset 0 0
Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Flash memory.
When this bit is set (one), the interrupt vectors are moved to the beginning of the Boot Loader section of
the flash. The actual address of the start of the Boot Flash section is determined by the BOOTSZ fuses.
Refer to the section Boot Loader Support – Read-While-Write Self-Programming for details. To avoid
unintentional changes of interrupt vector tables, a special write procedure must be followed to change the
IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the
cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If
IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is
unaffected by the automatic disabling.
Note: If interrupt vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If interrupt vectors are placed in the
Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from
the Boot Loader section. Refer to the section Boot Loader Support – Read-While-Write Self-Programming
for details on Boot Lock bits.
Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware
four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as
explained in the IVSEL description above. See Code Example below.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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