Datasheet

15.6.2. WDTCR – Watchdog Timer Control Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: WDTCR
Offset: 0x21
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x41
Bit 7 6 5 4 3 2 1 0
WDCE WDE WDP2 WDP1 WDP0
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be
disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description
of the WDE bit for a Watchdog disable procedure. In Safety Level 1 and 2, this bit must also be set when
changing the prescaler bits. Refer to Timed Sequences for Changing the Configuration of the Watchdog
Timer on page 72.
Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic
zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level
one. To disable an enabled Watchdog Timer, the following procedure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE
even though it is set to one before the disable operation starts.
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described
above. Refer to Timed Sequences for Changing the Configuration of the Watchdog Timer on page 72.
Bits 2:0 – WDPn: Watchdog Timer Prescaler 2, 1, and 0 [n = 2:0]
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer
is enabled. The different prescaling values and their corresponding Timeout Periods are shown in the
table below.
Table 15-2 Watchdog Timer Prescale Select
WDP2 WDP1 WDP0 Number of WDT Oscillator
Cycles
Typical
Time-out at
V
CC
= 3.0V
Typical
Time-out at
V
CC
= 5.0V
0 0 0 16K (16,384) 17.1ms 16.3ms
0 0 1 32K (32,768) 34.3ms 32.5ms
0 1 0 64K (65,536) 68.5ms 65ms
0 1 1 128K (131,072) 0.14s 0.13s
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
75