Datasheet

15.3. Internal Voltage Reference
ATmega64A features an internal bandgap reference. This reference is used for Brown-out Detection, and
it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is
generated from the internal bandgap reference.
15.3.1. Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. The start-up time
is given in the table in System and Reset Characteristics. To save power, the reference is not always
turned on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODEN Fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in
ACSR).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must
always allow the reference to start up before the output from the Analog Comparator or ADC is used. To
reduce power consumption in Power-down mode, the user can avoid the three conditions above to
ensure that the reference is turned off before entering Power-down mode.
Related Links
System and Reset Characteristics on page 418
15.4. Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This is the typical
value at V
CC
= 5V. See characterization data for typical values at other V
CC
levels. By controlling the
Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 15-2
Watchdog Timer Prescale Select on page 75. The WDR – Watchdog Reset – instruction resets the
Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset period
expires without another Watchdog Reset, the ATmega64A resets and executes from the Reset Vector.
For timing details on the Watchdog Reset, refer to Watchdog Reset on page 70.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, 3 different
safety levels are selected by the Fuses M103C and WDTON as shown in the table. Safety level 0
corresponds to the setting in ATmega103. There is no restriction on enabling the WDT in any of the safety
levels. Refer Timed Sequences for Changing the Configuration of the Watchdog Timer on page 72
details.
Table 15-1 WDT Configuration as a Function of the Fuse Settings of M103C and WDTON.
M103C WDTON Safety
Level
WDT Initial
State
How to Disable
the WDT
How to
Change Time-
out
Unprogrammed Unprogrammed 1 Disabled Timed sequence Timed
sequence
Unprogrammed Programmed 2 Enabled Always enabled Timed
sequence
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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