Datasheet

Figure 15-1 Reset Logic
MCU Control a nd S tatus
Re giste r (MCUCS R)
Brown-Out
Re se t Circuit
BODEN
BODLEVEL
Dela y Counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BUS
Clock
Ge ne ra tor
SP IKE
FILTER
Pull-up Res istor
JTRF
JTAG Re s et
Re giste r
Watchdog
Os cillator
SUT[1:0]
COUNTER RES ET
Watchdog
Timer
RES ET
Pull-up Res istor
PEN
Re se t Circuit
L
D Q
Q
Power-On Re s e t
Circuit
Related Links
IEEE 1149.1 (JTAG) Boundary-scan on page 340
15.2.1. Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is
defined in the table in System and Reset Characteristics. The POR is activated whenever V
CC
is below
the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a
failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on
Reset threshold voltage invokes the delay counter, which determines how long the device is kept in
RESET after V
CC
rise. The RESET signal is activated again, without any delay, when V
CC
decreases
below the detection level.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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