Datasheet

14.9.1. MCUCR – MCU Control Register
The MCU Control Register contains control bits for power management.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: MCUCR
Offset: 0x35
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x55
Bit 7 6 5 4 3 2 1 0
SE SM1 SM0 SM2
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 5 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose,
it is recommended to set the Sleep Enable (SE) bit to one just before the execution of the SLEEP
instruction.
Bits 4:3 – SMn: Sleep Mode n Select Bits [n=1:0]
These bits select between the five available sleep modes as shown in the table.
Table 14-2 Sleep Mode Select
SM2 SM1 SM0 Sleep Mode
0 0 0 Idle
0 0 1 ADC Noise Reduction
0 1 0 Power-down
0 1 1 Power-save
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Standby
(1)
1 1 0 Extended Standby
(1)
Note: 1. Standby mode is only available with external crystals or resonators.
Bit 2 – SM2: Sleep Mode Select Bit 2
Refer to SMn: Sleep Mode n Select Bits above.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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