Datasheet

13.10.1. XDIV – XTAL Divide Control Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
The XTAL Divide Control Register is used to divide the Source clock frequency by a number in the range
2 - 129. This feature can be used to decrease power consumption when the requirement for processing
power is low.
Name: XDIV
Offset: 0x3C
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x5C
Bit 7 6 5 4 3 2 1 0
XDIVEN XDIV6 XDIV5 XDIV4 XDIV3 XDIV2 XDIV1 XDIV0
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 – XDIVEN: XTAL Divide Enable
When the XDIVEN bit is written one, the clock frequency of the CPU and all peripherals (clk
I/O
, clk
ADC
,
clk
CPU
, clk
FLASH
) is divided by the factor defined by the setting of XDIV6 - XDIV0. This bit can be written
run-time to vary the clock frequency as suitable to the application.
Bits 6:0 – XDIVn: XTAL Divide Select Bits [n = 6:0]
These bits define the division factor that applies when the XDIVEN bit is set (one). If the value of these
bits is denoted d, the following formula defines the resulting CPU and peripherals clock frequency f
CLK
:

CLK
=
Source clock
129 – d
The value of these bits can only be changed when XDIVEN is zero. When XDIVEN is written to one, the
value written simultaneously into XDIV6:XDIV0 is taken as the division factor. When XDIVEN is written to
zero, the value written simultaneously into XDIV6:XDIV0 is rejected. As the divider divides the master
clock input to the MCU, the speed of all peripherals is reduced when a division factor is used.
When the system clock is divided, Timer/Counter0 can be used with Asynchronous clock only. The
frequency of the asynchronous clock must be lower than 1/4th of the frequency of the scaled down
Source clock. Otherwise, interrupts may be lost, and accessing the Timer/Counter0 registers may fail.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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