Datasheet

13. System Clock and Clock Options
13.1. Clock Systems and their Distribution
The figure below presents the principal clock systems in the AVR and their distribution. All of the clocks
need not be active at a given time. In order to reduce power consumption, the clocks to modules not
being used can be halted by using different sleep modes, as described in Power Management and Sleep
Modes on page 61. The clock systems are detailed in the following figure.
Figure 13-1 Clock Distribution
Gene ral I/O
Module s
Asynchronous
Timer/Counte r
ADC CP U Core RAM
clk
I/O
clk
ASY
AVR Clock
Control Unit
clk
CP U
Flash a nd
EEP ROM
clk
FLASH
clk
ADC
Source Clock
Wa tchdog Timer
Wa tchdog
Oscillator
Reset Logic
Clock
Multiplexer
Wa tchdog Clock
Calibrated RC
Oscillator
Timer/Counte r
Oscillator
Crys ta l
Oscillator
Low-Freque ncy
Crys ta l Os cilla tor
Externa l RC
Oscillator
Externa l Clock
13.1.1. CPU Clock – clk
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of
such modules are the General Purpose Register File, the Status Register and the Data memory holding
the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and
calculations.
13.1.2. I/O Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O
clock is also used by the External Interrupt module, but note that some external interrupts are detected by
asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also note that
address recognition in the TWI module is carried out asynchronously when clk
I/O
is halted, enabling TWI
address reception in all sleep modes.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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