Datasheet

Table 12-4 Wait States
(1)
SRWn1 SRWn0 Wait States
0 0 No wait-states
0 1 Wait one cycle during read/write strobe
1 0 Wait two cycles during read/write strobe
1 1 Wait two cycles during read/write and wait one cycle before driving
out new address
Note: 1. n = 0 or 1 (lower/upper sector). For further details of the timing and wait-states of the External
Memory Interface, see Figures 13-6 through Figures 13-9 for how the setting of the SRW bits affects the
timing.
Bit 1 – SRW11: Wait-state Select Bits for Upper Sector
The SRW11 and SRW10 (bit 6 in MCUCR) bits control the number of wait-states for the upper sector of
the external memory address space, see Table 12-4 Wait States(1) on page 50.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
50