Datasheet

12.7.6. XMCRA – External Memory Control Register A
Name: XMCRA
Offset: 0x6D
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
SRL2 SRL1 SRL0 SRW01 SRW00 SRW11
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 6:4 – SRLn: Wait-state Sector Limit [n = 2:0]
It is possible to configure different wait-states for different External Memory addresses. The external
memory address space can be divided in two sectors that have separate wait-state bits. The SRL2,
SRL1, and SRL0 bits select the split of the sectors, refer to the next table and Table 12-4 Wait States(1)
on page 50. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory
address space is treated as one sector. When the entire SRAM address space is configured as one
sector, the wait-states are configured by the SRW11 and SRW10 bits.
Table 12-3 Sector limits with different settings of SRL2:0
SRL2 SRL1 SRL0 Sector Limits
0 0 0 Lower sector = N/A
Upper sector = 0x1100 - 0xFFFF
0 0 1 Lower sector = 0x1100 - 0x1FFF
Upper sector = 0x2000 - 0xFFFF
0 1 0 Lower sector = 0x1100 - 0x3FFF
Upper sector = 0x4000 - 0xFFFF
0 1 1 Lower sector = 0x1100 - 0x5FFF
Upper sector = 0x6000 - 0xFFFF
1 0 0 Lower sector = 0x1100 - 0x7FFF
Upper sector = 0x8000 - 0xFFFF
1 0 1 Lower sector = 0x1100 - 0x9FFF
Upper sector = 0xA000 - 0xFFFF
1 1 0 Lower sector = 0x1100 - 0xBFFF
Upper sector = 0xC000 - 0xFFFF
1 1 1 Lower sector = 0x1100 - 0xDFFF
Upper sector = 0xE000 - 0xFFFF
Bits 3:2 – SRW0n: Wait-state Select Bits for Lower Sector [n = 1:0]
The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the external
memory address space, see table below.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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