Datasheet

Figure 32-11 External Memory Timing (SRWn1 = 1, SRWn0 = 1)
ALE
T1 T2 T3
Write
Rea d
WR
T7
A15:8
Addres s
Prev. a ddr.
DA7:0
Addres s Da taPrev. da ta
XX
RD
DA7:0 (XMBK = 0)
Data
Addres s
Syste m Clock (CLK
CP U
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
T4
T5
T6
The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the RAM (internal
or external).
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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