Datasheet

Symbol Parameter 4MHz Oscillator Variable Oscillator Unit
Min Max Min Max
6 t
AVWL
Address Valid to WR Low 235 1.0t
CLCL
-15 ns
7 t
LLWL
ALE Low to WR Low 115 130 0.5t
CLCL
-10
(2)
0.5t
CLCL
+5
(2)
ns
8 t
LLRL
ALE Low to RD Low 115 130 0.5t
CLCL
-10
(2)
0.5t
CLCL
+5
(2)
ns
9 t
DVRH
Data Setup to RD High 45 45 ns
10 t
RLDV
Read Low to Data Valid 190 1.0t
CLCL
-60 ns
11 t
RHDX
Data Hold After RD High 0 0 ns
12 t
RLRH
RD Pulse Width 235 1.0t
CLCL
-15 ns
13 t
DVWL
Data Setup to WR Low 105 0.5t
CLCL
-20
(1)
ns
14 t
WHDX
Data Hold After WR High 235 1.0t
CLCL
-15 ns
15 t
DVWH
Data Valid to WR High 250 1.0t
CLCL
ns
16 t
WLWH
WR Pulse Width 235 1.0t
CLCL
-15 ns
Note:
1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock,
XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock,
XTAL1.
Table 32-16 External Data Memory Characteristics, 2.7V - 5.5V, SRWn1 = 0, SRWn0 = 1
Symbol Parameter 4MHz Oscillator Variable Oscillator Unit
Min Max Min Max
0 1/t
CLCL
Oscillator Frequency 0.0 8 MHz
10 t
RLDV
Read Low to Data Valid 440 2.0t
CLCL
-60 ns
12 t
RLRH
RD Pulse Width 485 2.0t
CLCL
-15 ns
15 t
DVWH
Data Valid to WR High 500 2.0t
CLCL
ns
16 t
WLWH
WR Pulse Width 485 2.0t
CLCL
-15 ns
Table 32-17 External Data Memory Characteristics, 2.7V - 5.5V, SRWn1 = 1, SRWn0 = 0
Symbol Parameter 4MHz Oscillator Variable Oscillator Unit
Min Max Min Max
0 1/t
CLCL
Oscillator Frequency 0.0 8 MHz
10 t
RLDV
Read Low to Data Valid 690 3.0t
CLCL
-60 ns
12 t
RLRH
RD Pulse Width 735 3.0t
CLCL
-15 ns
15 t
DVWH
Data Valid to WR High 750 3.0t
CLCL
ns
16 t
WLWH
WR Pulse Width 735 3.0t
CLCL
-15 ns
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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