Datasheet

Table 32-8 SPI Timing Parameters
Description Mode Min Typ Max
1 SCK period Master See Table 24-5 Relationship between SCK and
Oscillator Frequency on page 242
ns
2 SCK high/low Master 50% duty cycle
3 Rise/Fall time Master 3.6
4 Setup Master 10
5 Hold Master 10
6 Out to SCK Master 0.5 • t
SCK
7 SCK to out Master 10
8 SCK to out high Master 10
9 SS low to out Slave 15
10 SCK period Slave 4 • tck
11 SCK high/low
(1)
Slave 2 • tck
12 Rise/Fall time Slave 1.6
13 Setup Slave 10
14 Hold Slave 10
15 SCK to out Slave 15
16 SCK to SS high Slave 20
17 SS high to tri-state Slave 10
18 SS low to SCK Salve 2 • tck
Note:
1. In SPI Programming mode the minimum SCK high/low period is:
- 2t
CLCL
for f
CK
< 12MHz
- 3t
CLCL
for f
CK
> 12MHz
Figure 32-7 SPI interface timing requirements (Master Mode)
MOS I
(Data Output)
SCK
(CP OL = 1)
MISO
(Data Input)
SCK
(CP OL = 0)
SS
MSB LS B
LSBMSB
...
...
6 1
2 2
34 5
8
7
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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