Datasheet

Note: 1. The timing requirements shown in the first figure in this section (i.e., t
DVXH
, t
XHXL
, and t
XLDX
)
also apply to reading operation.
Table 32-7 Parallel Programming Characteristics, VCC = 5V ± 10%
Symbol Parameter Min Typ Max Units
V
PP
Programming Enable Voltage 11.5 12.5 V
I
PP
Programming Enable Current 250 μA
t
DVXH
Data and Control Valid before XTAL1 High 67 ns
t
XLXH
XTAL1 Low to XTAL1 High 200 ns
t
XHXL
XTAL1 Pulse Width High 150 ns
t
XLDX
Data and Control Hold after XTAL1 Low 67 ns
t
XLWL
XTAL1 Low to WR Low 0 ns
t
XLPH
XTAL1 Low to PAGEL high 0 ns
t
PLXH
PAGEL low to XTAL1 high 150 ns
t
BVPH
BS1 Valid before PAGEL High 67 ns
t
PHPL
PAGEL Pulse Width High 150 ns
t
PLBX
BS1 Hold after PAGEL Low 67 ns
t
WLBX
BS2/1 Hold after WR Low 67 ns
t
PLWL
PAGEL Low to WR Low 67 ns
t
BVWL
BS1 Valid to WR Low 67 ns
t
WLWH
WR Pulse Width Low 150 ns
t
WLRL
WR Low to RDY/BSY Low 0 1 μs
t
WLRH
WR Low to RDY/BSY High
(1)
3.7 4.5 ms
t
WLRH_CE
WR Low to RDY/BSY High for Chip Erase
(2)
7.5 9 ms
t
XLOL
XTAL1 Low to OE Low 0 ns
t
BVDV
BS1 Valid to DATA valid 0 250 ns
t
OLDV
OE Low to DATA Valid 250 ns
t
OHDZ
OE High to DATA Tri-stated 250 ns
Note:
1. t
WLRH
is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write Lock Bits commands.
2. t
WLRH_CE
is valid for the Chip Erase command.
32.7. SPI Timing Characteristics
See figures below for details.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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