Datasheet

Symbol Parameter Condition Min Max Units
t
HD;STA
Hold Time (repeated) START
Condition
f
SCL
≤ 100kHz 4.0 – μs
f
SCL
> 100kHz 0.6 – μs
t
LOW
Low Period of the SCL Clock f
SCL
≤ 100kHz 4.7 – μs
f
SCL
> 100kHz 1.3 – μs
t
HIGH
High period of the SCL clock f
SCL
≤ 100kHz 4.0 – μs
f
SCL
> 100kHz 0.6 – μs
t
SU;STA
Set-up time for a repeated
START condition
f
SCL
≤ 100kHz 4.7 – μs
f
SCL
> 100kHz 0.6 – μs
t
HD;DAT
Data hold time f
SCL
≤ 100kHz 0 3.45 μs
f
SCL
> 100kHz 0 0.9 μs
t
SU;DAT
Data setup time f
SCL
≤ 100kHz 250 – ns
f
SCL
> 100kHz 100 – ns
t
SU;STO
Setup time for STOP condition f
SCL
≤ 100kHz 4.0 – μs
f
SCL
> 100kHz 0.6 – μs
t
BUF
Bus free time between a STOP
and START condition
f
SCL
≤ 100kHz 4.7 – μs
Note:
1. In ATmega64A, this parameter is characterized and not 100% tested.
2. Required only for f
SCL
> 100kHz.
3. C
b
= capacitance of one bus line in pF.
4. f
CK
= CPU clock frequency
5. This requirement applies to all ATmega64A Two-wire Serial Interface operation. Other devices
connected to the Two-wire Serial Bus need only obey the general f
SCL
requirement.
Figure 32-3 Two-wire Serial Bus Timing
t
SU;S TA
t
LOW
t
HIGH
t
LOW
t
of
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;S TO
t
BUF
SCL
SDA
t
r
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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