Datasheet

Figure 31-12 State Machine Sequence for Changing/Reading the Data Word
Test-Logic-Res e t
Run-Te s t/Idle
Shift-DR
Exit1-DR
Pause -DR
Exit2-DR
Update -DR
Se le ct-IR S can
Ca pture-IR
Shift-IR
Exit1-IR
Pause -IR
Exit2-IR
Update -IR
Se le ct-DR S can
Ca pture-DR
0
1
0
1 1 1
0 0
0 0
1 1
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
00
11
Related Links
Page Size on page 387
31.10.11. Virtual Flash Page Load Register
The Virtual Flash Page Load Register is a virtual scan chain with length equal to the number of bits in one
Flash page. Internally the Shift Register is 8-bit, and the data are automatically transferred to the Flash
page buffer byte by byte. Shift in all instruction words in the page, starting with the LSB of the first
instruction in the page and ending with the MSB of the last instruction in the page. This provides an
efficient way to load the entire Flash page buffer before executing Page Write.
Atmel ATmega64A [DATASHEET]
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