Datasheet

1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the
XTAL1 pin.
2. V
CC
- 0.3 < AV
CC
< V
CC
+ 0.3V, however, AV
CC
should always be within 2.7 - 5.5V.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation
(in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip
Erase operation turns the content of every memory location in both the Program and EEPROM arrays
into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the
Serial Clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
ck
< 12MHz, 3 CPU clock cycles for f
ck
≥ 12MHz
High: > 2 CPU clock cycles for f
ck
< 12MHz, 3 CPU clock cycles for f
ck
≥ 12MHz
31.9.1. SPI Serial Programming Algorithm
When writing serial data to the ATmega64A, data is clocked on the rising edge of SCK.
When reading data from the ATmega64A, data is clocked on the falling edge of SCK. Refer to Figure
31-8 Serial Programming Waveforms on page 399 for timing details.
To program and verify the ATmega64A in the SPI Serial Programming mode, the following sequence is
recommended (See four byte instruction formats in Figure 31-8 Serial Programming Waveforms on page
399):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the
programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be
given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”.
As an alternative to using the RESET signal, PEN can be held low during Power-on Reset while
SCK is set to “0”. In this case, only the PEN value at Power-on Reset is important. If the
programmer cannot guarantee that SCK is held low during power-up, the PEN method cannot be
used. The device must be powered down in order to commence normal operation when using this
method.
2. Wait for at least 20ms and enable SPI Serial Programming by sending the Programming Enable
serial instruction to pin MOSI.
3. The SPI Serial Programming instructions will not work if the communication is out of
synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte
of the Programming Enable instruction. Whether the echo is correct or not, all 4 bytes of the
instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and
issue a new Programming Enable command.
4. The Flash is programmed one page at a time (see Page Size). The memory page is loaded one
byte at a time by supplying the 7 LSB of the address and data together with the Load Program
Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded
before data high byte is applied for given address. The Program Memory Page is stored by loading
the Write Program Memory Page instruction with the 8MSB of the address. If polling is not used,
the user must wait at least t
WD_FLASH
before issuing the next page. (See Table 31-14 Minimum Wait
Delay Before Writing the Next Flash or EEPROM Location, VCC = 5V ± 10% on page 398).
Note: 1. If other commands than polling (read) are applied before any write operation (Flash,
EEPROM, Lock bits, Fuses) is completed, may result in incorrect programming.
5. The EEPROM array is programmed one byte at a time by supplying the address and data together
with the appropriate Write instruction. An EEPROM memory location is first automatically erased
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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