Datasheet

31.7. Parallel Programming Parameters, Pin Mapping, and Commands
This section describes how to parallel program and verify Flash Program memory, EEPROM Data
memory, Memory Lock bits, and Fuse bits in the device. Pulses are assumed to be at least 250ns unless
otherwise noted.
31.7.1. Signal Names
In this section, some pins of this device are referenced by signal names describing their functionality
during parallel programming, refer to the following figure and table Pin Name Mapping in this section.
Pins not described in the following table are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit
coding is shown in Table 31-11 XA1 and XA0 Coding on page 395.
When pulsing WR or OE, the command loaded determines the action executed. The different Commands
are shown in Table 31-12 Command Byte Bit Coding on page 395.
Figure 31-6 Parallel Programming
VCC
+5V
GND
XTAL1
PD1
PD2
PD3
PD4
PD5
PD6
DATA
RESET
PB7-PB0
PD7
+12 V
BS1
XA0
XA1
OE
RDY/BSY
WR
PAGEL
PA0
BS2
AVCC
+5V
Table 31-9 Pin Name Mapping
Signal Name in
Programming Mode
Pin Name I/O Function
RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for new
command
OE PD2 I Output Enable (Active low)
WR PD3 I Write Pulse (Active low)
BS1 PD4 I Byte Select 1 (“0” selects Low byte, “1” selects High byte)
Atmel ATmega64A [DATASHEET]
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