Datasheet

Figure 12-6 External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0)
ALE
T1 T2 T3
Write
Re a d
WR
T4
A15:8
Addre s s
Prev. a ddr.
DA7:0
Addre s s DataPrev. data
XX
RD
DA7:0 (XMBK = 0)
Data
Prev. data Addres s
DataPrev. data Addres s
DA7:0 (XMBK = 1)
Sys te m Clock (CLK
CPU
)
XXXXX
XXXXXXXX
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction accesses the
RAM (internal or external).
Figure 12-7 External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1
(1)
ALE
T1 T2 T3
Write
Re a d
WR
T5
A15:8
Addre s s
Prev. a ddr.
DA7:0
Addre s s Da taPrev. da ta
XX
RD
DA7:0 (XMBK = 0)
Data
Prev. da ta Addre s s
DataPrev. da ta Addre s s
DA7:0 (XMBK = 1)
Sys te m Clock (CLK
CPU
)
T4
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
SRW00 (lower sector).
The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal or external).
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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