Datasheet

Loader, and further software updates might be impossible. If it is not necessary to change the Boot
Loader software itself, it is recommended to program the Boot Lock bit11 to protect the Boot Loader
software from any internal software changes.
30.8.6. Prevent Reading the RWW Section During Self-Programming
During Self-Programming (either Page Erase or Page Write), the RWW section is always blocked for
reading. The user software itself must prevent that this section is addressed during the self programming
operation. The RWWSB in the SPMCSR (SPMCSR.RWWSB) will be set as long as the RWW section is
busy. During Self-Programming the Interrupt Vector table should be moved to the BLS as described in
Interrupts chapter, or the interrupts must be disabled. Before addressing the RWW section after the
programming is completed, the user software must clear the SPMCSR.RWWSB by writing the
SPMCSR.RWWSRE. Refer to Simple Assembly Code Example for a Boot Loader on page 376 for an
example.
Related Links
Interrupts on page 77
30.8.7. Setting the Boot Loader Lock Bits by SPM
To set the Boot Loader Lock bits and general Lock Bits, write the desired data to R0, write “0x0001001” to
SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The only accessible lock bits
are the Boot Lock bits that may prevent the Application and Boot Loader section from any software
update by the MCU.
Bit 7 6 5 4 3 2 1 0
Rd – – – – – – LB2 LB1
BLB01
BLB02
BLB11
BLB12
1
1 1 1
The tables in Boot Loader Lock Bits on page 369 show how the different settings of the Boot Loader bits
affect the Flash access.
If bits 5:2 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an SPM instruction is
executed within four cycles after BLBSET and SPMEN are set in SPMCSR. The Z-pointer don’t care
during this operation, but for future compatibility it is recommended to load the Z-pointer with 0x0001
(same as used for reading the Lock bits). For future compatibility it is also recommended to set bits 7, 6, 1
and 0 in R0 to “1” when writing the Lock bits. When programming the Lock bits the entire Flash can be
read during the operation.
30.8.8. EEPROM Write Prevents Writing to SPMCSR
An EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock
bits from software will also be prevented during the EEPROM write operation. It is recommended that the
user checks the status bit (EEWE) in the EECR Register (EECR.EEWE) and verifies that the bit is
cleared before writing to the SPMCSR Register.
30.8.9. Reading the Fuse and Lock Bits from Software
It is possible to read both the Fuse and Lock Bits from software. To read the Lock Bits, load the Z-pointer
with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed
within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR, the value of the Lock
Bits will be loaded in the destination register. The BLBSET and SPMEN bits will auto-clear upon
completion of reading the Lock Bits or if no LPM instruction is executed within three CPU cycles or no
SPM instruction is executed within four CPU cycles. When BLBSET and SPMEN are cleared, LPM will
work as described in the Instruction set Manual.
Bit 7 6 5 4 3 2 1 0
Rd – – – – – – LB2 LB1
BLB01
BLB02
BLB11
BLB12
–
– LB2
LB1
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
374