Datasheet

• Data (address) hold time after G low (
TH
).
The External Memory Interface is designed to guaranty minimum address hold time after G is asserted
low of th = 5ns. Refer to t
LAXX_LD
/t
LLAXX_ST
in all the tables in section External Data Memory Timing. The
D-to-Q propagation delay (t
PD
) must be taken into consideration when calculating the access time
requirement of the external component. The data setup time before G low (t
SU
) must not exceed address
valid to ALE low (t
AVLLC
) minus PCB wiring delay (dependent on the capacitive load).
Figure 12-5 External SRAM Connected to the Atmel AVR
D[7:0]
A[7:0]
A[15:8]
RD
WR
SRAM
D Q
G
AD7:0
ALE
A15:8
RD
WR
AVR
12.6.6. Pull-up and Bus-keeper
The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to one. To
reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port
register to zero before entering sleep.
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be disabled and
enabled in software as described in XMCRB on page 51. When enabled, the bus-keeper will ensure a
defined logic level (zero or one) on the AD7:0 bus when these lines would otherwise be tri-stated by the
XMEM interface.
12.6.7. Timing
External Memory devices have different timing requirements. To meet these requirements, the Atmel AVR
ATmega64A XMEM interface provides four different wait-states as shown in Table 12-4 Wait States(1) on
page 50. It is important to consider the timing specification of the External Memory device before
selecting the wait-state. The most important parameters are the access time for the external memory
compared to the set-up requirement of the ATmega64A. The access time for the External Memory is
defined to be the time from receiving the chip select/address until the data of this address actually is
driven on the bus. The access time cannot exceed the time from the ALE pulse must be asserted low until
data is stable during a read sequence (See t
LLRL
+ t
RLRH
- t
DVRH
in the tables in section External Data
Memory Timing). The different wait-states are set up in software. As an additional feature, it is possible to
divide the external memory space in two sectors with individual wait-state settings. This makes it possible
to connect two different memory devices with different timing requirements to the same XMEM interface.
For XMEM interface timing details, please refer to the tables and figures in section External Data Memory
Timing.
Note that the XMEM interface is asynchronous and that the waveforms in the following figures are related
to the internal system clock. The skew between the internal and external clock (XTAL1) is not guaranteed
(varies between devices temperature, and supply voltage). Consequently, the XMEM interface is not
suited for synchronous operation.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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