Datasheet

29.16.1. OCDR – On-chip Debug Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: OCDR
Offset: 0x22
Reset: 0x20
Property: When addressing I/O Registers as data space the offset address is 0x42
Bit 7 6 5 4 3 2 1 0
IDRD/OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 – IDRD/OCDR7: USART Receive Complete
The OCDR Register provides a communication channel from the running program in the microcontroller
to the debugger. The CPU can transfer a byte to the debugger by writing to this location. At the same
time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate to the debugger that the
register has been written. When the CPU reads the OCDR Register the 7 LSB will be from the OCDR
Register, while the MSB is the IDRD bit. The debugger clears the IDRD bit when it has read the
information.
In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR Register
can only be accessed if the OCDEN fuse is programmed, and the debugger enables access to the OCDR
Register. In all other cases, the standard I/O location is accessed.
• Bit 7 is MSB
• Bit 1 is LSB
Refer to the debugger documentation for further information on how to use this register.
Bits 6:0 – OCDRn: On-chip Debug Register n [n = 6:0]
Atmel ATmega64A [DATASHEET]
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