Datasheet

Step Actions ADCEN DAC MUXEN HOLD PRECH PA3.
Data
PA3.
Control
PA3.
Pullup_
Enable
7 1 0x200 0x08 0 1 0 0 0
8 1 0x200 0x08 1 1 0 0 0
9 1 0x143 0x08 1 1 0 0 0
10 1 0x143 0x08 1 0 0 0 0
11 Verify the
COMP bit
scanned out to
be 1
1 0x200 0x08 1 1 0 0 0
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock frequency. As the
algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at least five times the
number of scan bits divided by the maximum hold time, t
hold,max
29.14. ATmega64A Boundary-scan Order
The table below shows the Scan order between TDI and TDO when the Boundary-scan Chain is selected
as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows
the pin-out order as far as possible. Therefore, the bits of Port A are scanned in the opposite bit order of
the other ports.
Exceptions from the rules are the scan chains for the analog circuits, which constitute the most significant
bits of the scan chain regardless of which physical pin they are connected to. In Figure 29-5 Boundary-
scan Cell for Bi-directional Port Pin with Pull-Up Function. on page 345, PXn. Data corresponds to FF0,
PXn. Control corresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port
C is not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled.
Table 29-7 ATmega64A Boundary-scan Order
Bit Number Signal Name Module
204 AC_IDLE Comparator
203 ACO
202 ACME
201 AINBG
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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