Datasheet

The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRELOAD, and
EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be used for testing the
Printed Circuit Board. Initial scanning of the data register path will show the ID-code of the device, since
IDCODE is the default JTAG instruction. It may be desirable to have the AVR device in reset during test
mode. If not reset, inputs to the device may be determined by the scan operations, and the internal
software may be in an undetermined state when exiting the test mode. Entering Reset, the outputs of any
Port Pin will instantly enter the high impedance state, making the HIGHZ instruction redundant. If needed,
the BYPASS instruction can be issued to make the shortest possible scan chain through the device. The
device can be set in the Reset state either by pulling the external RESET pin low, or issuing the
AVR_RESET instruction with appropriate setting of the Reset Data Register.
The EXTEST instruction is used for sampling external pins and loading output pins with data. The data
from the output latch will be driven out on the pins as soon as the EXTEST instruction is loaded into the
JTAG IR-register. Therefore, the SAMPLE/PRELOAD should also be used for setting initial values to the
scan ring, to avoid damaging the board when issuing the EXTEST instruction for the first time. SAMPLE/
PRELOAD can also be used for taking a snapshot of the external pins during normal operation of the
part.
The JTAGEN fuse must be programmed and the JTD bit in the I/O register MCUCSR must be cleared to
enable the JTAG Test Access Port.
When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher than the
internal chip frequency is possible. The chip clock is not required to run.
29.11. Data Registers
The data registers relevant for Boundary-scan operations are:
• Bypass Register
• Device Identification Register
• Reset Register
• Boundary-scan Chain
29.11.1. Bypass Register
The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as
path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The
Bypass Register can be used to shorten the scan chain on a system when the other devices are to be
tested.
29.11.2. Device Identification Register
The figure below shows the structure of the Device Identification Register.
Figure 29-3 The format of the Device Identification Register
Version
Part Number
Manufacturer ID
1
4 bits
16 bits
11 bits
1-bit
0
LSB
MSB
31
28
27
12 11
1
Bit
Device ID
29.11.2.1. Version
Version is a 4-bit number identifying the revision of the component. The JTAG version number follows the
revision of the device, and wraps around at revision P (0xF). Revision A and Q is 0x0, revision B and R is
0x1 and so on.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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