Datasheet

29.8. Using the JTAG Programming Capabilities
Programming of AVR parts via JTAG is performed via the four-pin JTAG port, TCK, TMS, TDI, and TDO.
These are the only pins that need to be controlled/observed to perform JTAG programming (in addition to
power pins). It is not required to apply 12V externally. The JTAGEN fuse must be programmed and the
JTD bit in the MCUCSR Register must be cleared to enable the JTAG Test Access Port.
The JTAG programming capability supports:
• Flash programming and verifying
• EEPROM programming and verifying
• Fuse programming and verifying
• Lock bit programming and verifying
The Lock bit security is exactly as in Parallel Programming mode. If the Lock bits LB1 or LB2 are
programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a security
feature that ensures no back-door exists for reading out the content of a secured device.
The details on programming through the JTAG interface and programming specific JTAG instructions are
given in the section Programming Via the JTAG Interface.
Related Links
Programming Via the JTAG Interface on page 400
29.9. Bibliography
For more information about general Boundary-scan, the following literature can be consulted:
• IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan Architecture,
IEEE, 1993
• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley, 1992
29.10. IEEE 1149.1 (JTAG) Boundary-scan
29.10.1. Features
• JTAG (IEEE std. 1149.1 Compliant) Interface
• Boundary-scan Capabilities According to the JTAG Standard
• Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections
• Supports the Optional IDCODE Instruction
• Additional Public AVR_RESET Instruction to Reset the AVR
29.10.2. System Overview
The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O
pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip
connections. At system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO
signals to form a long Shift Register. An external controller sets up the devices to drive values at their
output pins, and observe the input values received from other devices. The controller compares the
received data with the expected result. In this way, Boundary-scan provides a mechanism for testing
interconnections and integrity of components on Printed Circuits Boards by using the four TAP signals
only.
Atmel ATmega64A [DATASHEET]
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