Datasheet

28.8.6. ADCH – ADC Data Register High (ADLAR=1)
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: ADCH
Offset: 0x05
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x25
Bit 7 6 5 4 3 2 1 0
ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 – ADC9: ADC Conversion Result
Bit 6 – ADC8: ADC Conversion Result
Bit 5 – ADC7: ADC Conversion Result
Bit 4 – ADC6: ADC Conversion Result
Bit 3 – ADC5: ADC Conversion Result
Bit 2 – ADC4: ADC Conversion Result
Bit 1 – ADC3: ADC Conversion Result
Bit 0 – ADC2: ADC Conversion Result
Refer to ADCL on page 330
Atmel ATmega64A [DATASHEET]
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