Datasheet

Figure 28-9 ADC Power Connections
VCC
GND
100nF
(ADC0) P F0
(ADC7) P F7
(ADC1) P F1
(ADC2) P F2
(ADC3) P F3
(ADC4) P F4
(ADC5) P F5
(ADC6) P F6
AREF
GND
AVCC
52
53
54
55
56
57
58
59
60
6161
6262
6363
6464
1
51
PEN
(AD0) PA0
10µ
H
28.6.3. Offset Compensation Schemes
The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements
as much as possible. The remaining offset in the analog path can be measured directly by selecting the
same channel for both differential inputs. This offset residue can be then subtracted in software from the
measurement results. Using this kind of software based offset correction, offset on any channel can be
reduced below one LSB.
28.6.4. ADC Accuracy Definitions
An n-bit single-ended ADC converts a voltage linearly between GND and V
REF
in 2
n
steps (LSBs). The
lowest code is read as 0, and the highest code is read as 2
n
-1.
Several parameters describe the deviation from the ideal behavior:
• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5
LSB). Ideal value: 0 LSB.
Atmel ATmega64A [DATASHEET]
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