Datasheet

25.11.4. UCSRmC – USART Control and Status Register C
Note: This register is not available in ATmega103 compatibility mode.
Name: UCSRmC
Offset: 0x20
Reset: 0x06
Property: When addressing I/O Registers as data space the offset address is 0x40
Bit 7 6 5 4 3 2 1 0
UMSELm UPMm1 UPMm0 USBSm UCSZm1 UCSZm0 UCPOLm
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 1 0
Bit 6 – UMSELm: Mode Select
This bit selects between Asynchronous and Synchronous mode of operation.
Table 25-8 UMSEL Bit Settings
UMSEL Bit Settings Mode
0 Asynchronous Operation
1 Synchronous Operation
Bits 5:4 – UPMmn: Parity Mode [n = 1:0]
UPMm1 and UPMm0 bits enable and set type of parity generation and check. If enabled, the Transmitter
will automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMm0 setting. If a
mismatch is detected, the UPEm flag in UCSRmA will be set.
Table 25-9 UPM Bits Settings
UPMm1 UPMm0 ParityMode
0 0 Disabled
0 1 Reserved
1 0 Enabled, Even Parity
1 1 Enabled, Odd Parity
Bit 3 – USBSm: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this
setting.
Table 25-10 USBS Bit Settings
USBSm Stop Bit(s)
0 1-bit
1 2-bit
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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