Datasheet

The following figure shows the parallel instruction fetches and instruction executions enabled by the
Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to
obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per
clocks, and functions per power-unit.
Figure 11-4 The Parallel Instruction Fetches and Instruction Executions
clk
1s t Ins truction Fe tch
1s t Instruction Execute
2nd Ins truction Fe tch
2nd Ins truction Execute
3rd Ins truction Fetch
3rd Ins truction Execute
4th Ins truction Fetch
T1 T2 T3 T4
CPU
The next figure shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination
register.
Figure 11-5 Single Cycle ALU Operation
Total Exe cution Time
Re gis te r Operands Fetch
ALU Opera tion Execute
Re sult Write Back
T1 T2 T3 T4
clk
CPU
11.7. Reset and Interrupt Handling
The Atmel AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned
individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the
Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may
be automatically disabled when Boot Lock Bits BLB02 or BLB12 are programmed. This feature improves
software security. See the section Memory Programming for details.
The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt
Vectors. The complete list of Vectors is shown in Interrupts . The list also determines the priority levels of
the different interrupts. The lower the address the higher is the priority level. RESET has the highest
priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the
start of the boot Flash section by setting the Interrupt Vector Select (IVSEL) bit in the MCU Control
Register (MCUCR). Refer to Interrupts for more information. The Reset Vector can also be moved to the
start of the boot Flash section by programming the BOOTRST Fuse, see Boot Loader Support – Read-
While-Write Self-Programming.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The
user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then
Atmel ATmega64A [DATASHEET]
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