Datasheet

25.11.2. UCSRmA – USART Control and Status Register A
Name: UCSRmA
Offset: 0x9B
Reset: 0x20
Property: –
Bit 7 6 5 4 3 2 1 0
RXCm TXCm UDREm FEm DORm UPEm U2Xm MPCMm
Access
R R/W R R R R R/W R/W
Reset 0 0 1 0 0 0 0 0
Bit 7 – RXCm: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is
empty (that is, does not contain any unread data). If the receiver is disabled, the receive buffer will be
flushed and consequently the RXCm bit will become zero. The RXCm flag can be used to generate a
Receive Complete interrupt (see description of the RXCIEm bit).
Bit 6 – TXCm: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are
no new data currently present in the transmit buffer (UDRm). The TXCm flag bit is automatically cleared
when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The
TXCm flag can generate a Transmit Complete interrupt (see description of the TXCIEm bit).
Bit 5 – UDREm: USART Data Register Empty
The UDREm flag indicates if the transmit buffer (UDRm) is ready to receive new data. If UDREm is one,
the buffer is empty, and therefore ready to be written. The UDREm flag can generate a Data Register
Empty interrupt (see description of the UDRIEm bit).
UDREm is set after a reset to indicate that the Transmitter is ready.
Bit 4 – FEm: Frame Error
This bit is set if the next character in the receive buffer had a Frame Error when received, that is, when
the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer
(UDRm) is read. The FEm bit is zero when the stop bit of received data is one. Always set this bit to zero
when writing to UCSRmA.
Bit 3 – DORm: Data OverRun
This bit is set if a Data OverRun condition is detected. A data overrun occurs when the receive buffer is
full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is
detected. This bit is valid until the receive buffer (UDRm) is read. Always set this bit to zero when writing
to UCSRmA.
Bit 2 – UPEm: Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received and the parity
checking was enabled at that point (UPMm1 = 1). This bit is valid until the receive buffer (UDRm) is read.
Always set this bit to zero when writing to UCSRmA.
Bit 1 – U2Xm: Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous
operation.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
267