Datasheet

Figure 11-3 The X-, Y- and Z-Registers
15
XH
XL
0
X-re giste r
7
0
7
0
R27 (0x1B)
R26 (0x1A)
15
YH
YL
0
Y-re giste r
7
0
7
0
R29 (0x1D)
R28 (0x1C)
15
ZH
ZL
0
Z-regis te r
7
0
7
0
R31 (0x1F)
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the Instruction Set Reference for details).
11.5. Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return
addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the
Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory
locations. This implies that a Stack PUSH command decreases the Stack Pointer. If software reads the
Program Counter from the Stack after a call or an interrupt, unused bits (bit 15) should be masked out.
The Stack Pointer points to the data SRAM Stack area where the subroutine and interrupt Stacks are
located. This Stack space in the data SRAM must be defined by the program before any subroutine calls
are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack
Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is
decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt.
The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction,
and it is incremented by two when data is popped from the Stack with return from subroutine RET or
return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually
used is implementation dependent. Note that the data space in some implementations of the AVR
architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.
Bit
15
14
13
12
11
10
9
8
0x3E
S P15
S P14
S P13
S P12
S P11
S P10
S P9
S P8
S PH
0x3D
S P7
S P6
S P5
S P4
S P3
S P2
S P1
S P0
S PL
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
11.6. Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The Atmel AVR CPU
is driven by the CPU clock clk
CPU
, directly generated from the selected clock source for the chip. No
internal clock division is used.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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