Datasheet

does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be
flushed and consequently the RXC bit will become zero.
When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive Complete
Interrupt will be executed as long as the RXC Flag is set (provided that global interrupts are enabled).
When interrupt-driven data reception is used, the receive complete routine must read the received data
from UDR in order to clear the RXC Flag, otherwise a new interrupt will occur once the interrupt routine
terminates.
25.7.4. Receiver Error Flags
The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity Error
(UPE). All can be accessed by reading UCSRA. Common for the error flags is that they are located in the
receive buffer together with the frame for which they indicate the error status. Due to the buffering of the
error flags, the UCSRA must be read before the receive buffer (UDR), since reading the UDR I/O location
changes the buffer read location. Another equality for the error flags is that they can not be altered by
software doing a write to the flag location. However, all flags must be set to zero when the UCSRA is
written for upward compatibility of future USART implementations. None of the error flags can generate
interrupts.
The Frame Error (FE) Flag indicates the state of the first stop bit of the next readable frame stored in the
receive buffer. The FE Flag is zero when the stop bit was correctly read (as one), and the FE Flag will be
one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions,
detecting break conditions and protocol handling. The FE Flag is not affected by the setting of the USBS
bit in UCSRC since the Receiver ignores all, except for the first, stop bits. For compatibility with future
devices, always set this bit to zero when writing to UCSRA.
The Data OverRun (DOR) Flag indicates data loss due to a Receiver buffer full condition. A Data
OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the
Receive Shift Register, and a new start bit is detected. If the DOR Flag is set there was one or more serial
frame lost between the frame last read from UDR, and the next frame read from UDR. For compatibility
with future devices, always write this bit to zero when writing to UCSRA. The DOR Flag is cleared when
the frame received was successfully moved from the Shift Register to the receive buffer.
The Parity Error (UPE) Flag indicates that the next frame in the receive buffer had a parity error when
received. If parity check is not enabled the UPE bit will always be read zero. For compatibility with future
devices, always set this bit to zero when writing to UCSRA. For more details, refer to Parity Bit
Calculation on page 251 and Parity Checker on page 257.
25.7.5. Parity Checker
The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to
be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the
parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame.
The result of the check is stored in the receive buffer together with the received data and stop bits. The
Parity Error (UPE) Flag can then be read by software to check if the frame had a parity error.
The UPE bit is set if the next character that can be read from the receive buffer had a parity error when
received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive
buffer (UDR) is read.
25.7.6. Disabling the Receiver
In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions
will therefore be lost. When disabled (i.e., the RXEN is set to zero) the Receiver will no longer override
the normal function of the RxD port pin. The Receiver buffer FIFO will be flushed when the Receiver is
disabled. Remaining data in the buffer will be lost.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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