Datasheet

UCSRB &= ~(1<<TXB8);
if ( data & 0x0100 )
UCSRB |= (1<<TXB8);
/* Put data into buffer, sends the data */
UDR = data;
}
Note: 1. These transmit functions are written to be general functions. They can be
optimized if the contents of the UCSRB is static. For example, only the TXB8 bit of the
UCSRB Register is used after initialization. For I/O registers located in extended I/O map,
“IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with
instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with
“SBRS”, “SBRC”, “SBR”, and “CBR”.
The ninth bit can be used for indicating an address frame when using multi processor
communication mode or for other protocol handling as for example synchronization.
25.6.3. Transmitter Flags and Interrupts
The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDRE) and
Transmit Complete (TXC). Both flags can be used for generating interrupts.
The Data Register Empty (UDRE) Flag indicates whether the transmit buffer is ready to receive new data.
This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be
transmitted that has not yet been moved into the Shift Register. For compatibility with future devices,
always write this bit to zero when writing the UCSRA Register.
When the Data Register empty Interrupt Enable (UDRIE) bit in UCSRB is written to one, the USART Data
Register Empty Interrupt will be executed as long as UDRE is set (provided that global interrupts are
enabled). UDRE is cleared by writing UDR. When interrupt-driven data transmission is used, the Data
Register empty Interrupt routine must either write new data to UDR in order to clear UDRE or disable the
Data Register empty Interrupt, otherwise a new interrupt will occur once the interrupt routine terminates.
The Transmit Complete (TXC) Flag bit is set one when the entire frame in the transmit Shift Register has
been shifted out and there are no new data currently present in the transmit buffer. The TXC Flag bit is
automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one
to its bit location. The TXC Flag is useful in half-duplex communication interfaces (like the RS485
standard), where a transmitting application must enter Receive mode and free the communication bus
immediately after completing the transmission.
When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART Transmit
Complete Interrupt will be executed when the TXC Flag becomes set (provided that global interrupts are
enabled). When the transmit complete interrupt is used, the interrupt handling routine does not have to
clear the TXC Flag, this is done automatically when the interrupt is executed.
25.6.4. Parity Generator
The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled (UPM1
= 1), the Transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the
frame that is sent.
25.6.5. Disabling the Transmitter
The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongoing and
pending transmissions are completed (i.e., when the Transmit Shift Register and Transmit Buffer Register
do not contain data to be transmitted). When disabled, the Transmitter will no longer override the TxD pin.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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