Datasheet

25. USART

25.1. Features

• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation

• Master or Slave Clocked Synchronous Operation

• High Resolution Baud Rate Generator

• Supports Serial Frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits

• Odd or Even Parity Generation and Parity Check Supported by Hardware

• Data OverRun Detection

• Framing Error Detection

• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

• Multi-processor Communication Mode

• Double Speed Asynchronous Communication Mode

25.1.1. Dual USART

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly

flexible serial communication device. The ATmega64A has two USARTs, USART0 and USART1. The

functionality for both USARTs is described below. USART0 and USART1 have different I/O registers as

shown in Register Summary. Note that in ATmega103 compatibility mode, USART1 is not available,

neither is the UBRR0H or UCRS0C Registers. This means that in ATmega103 compatibility mode, the

ATmega64A supports asynchronous operation of USART0 only.