Datasheet

Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See Phase Correct PWM Mode on page 222 for
more details.
Bit 3 – WGM21: Waveform Generation Mode [n=0:1]
Refer to WGM20 above.
Bits 2:0 – CS2n: Clock Select [n = 2:0]
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 22-6 Clock Select Bit Description
CS22 CS21 CS20 Description
0 0 0 No clock source (Timer/Counter stopped).
0 0 1 clk
I/O
/1 (No prescaling)
0 1 0 clk
I/O
/8 (From prescaler)
0 1 1 clk
I/O
/64 (From prescaler)
1 0 0 clkI/O/256 (From prescaler)
1 0 1 clk
I/O
/1024 (From prescaler)
1 1 0 External clock source on T2 pin. Clock on falling edge.
1 1 1 External clock source on T2 pin. Clock on falling edge.
If external pin modes are used for the Timer/Counter2, transitions on the T2 pin will clock the counter
even if the pin is configured as an output. This feature allows software control of the counting.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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