Datasheet

Bits 5:4 – COM2n: Compare Match Output Mode [n = 1:0]
These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM21:0 bits are set,
the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that
the Data Direction Register (DDR) bit corresponding to the OC2 pin must be set in order to enable the
output driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit
setting. The following table shows the COM21:0 bit functionality when the WGM21:0 bits are set to a
normal or CTC mode (non-PWM).
Table 22-3 Compare Output Mode, Non-PWM Mode
COM21 COM20 Description
0 0 Normal port operation, OC2 disconnected.
0 1 Toggle OC2 on Compare Match
1 0 Clear OC2 on Compare Match
1 1 Set OC2 on Compare Match
The next table shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode.
Table 22-4 Compare Output Mode, Fast PWM Mode
(1)
COM21 COM20 Description
0 0 Normal port operation, OC2 disconnected.
0 1 Reserved
1 0 Clear OC2 on Compare Match, set OC2 at BOTTOM,
(non-inverting mode)
1 1 Set OC2 on Compare Match, clear OC2 at BOTTOM,
(inverting mode)
Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare
Match is ignored, but the set or clear is done at BOTTOM. See Fast PWM Mode on page 221 for more
details.
The table below shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct
PWM mode.
Table 22-5 Compare Output Mode, Phase Correct PWM Mode
(1)
COM21 COM20 Description
0 0 Normal port operation, OC2 disconnected.
0 1 Reserved
1 0 Clear OC2 on Compare Match when up-counting. Set OC2 on Compare Match when
downcounting.
1 1 Set OC2 on Compare Match when up-counting. Clear OC2 on Compare Match when
downcounting.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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