Datasheet

upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the
operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope
operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are
preferred for motor control applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode
the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it
changes the count direction. The TCNT2 value will be equal to MAX for one timer clock cycle. The timing
diagram for the phase correct PWM mode is shown on the figure below. The TCNT2 value is in the timing
diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-
inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent
compare matches between OCR2 and TCNT2.
Figure 22-7 Phase Correct PWM Mode, Timing Diagram
TOVn Interrupt Flag S e t
OCn Interrupt Flag S e t
1 2 3
TCNTn
Pe riod
OCn
OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
OCRn Update
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt
Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin.
Setting the COM21:0 bits to 2 will produce a non-inverted PWM. An inverted PWM output can be
generated by setting the COM21:0 to 3 (refer to Table 22-5 Compare Output Mode, Phase Correct PWM
Mode(1) on page 227). The actual OC2 value will only be visible on the port pin if the data direction for
the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2 Register at
the Compare Match between OCR2 and TCNT2 when the counter increments, and setting (or clearing)
the OC2 Register at Compare Match between OCR2 and TCNT2 when the counter decrements. The
PWM frequency for the output when using phase correct PWM can be calculated by the following
equation:

OCnPCPWM
=

clk_I/O
  510
The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256 or 1024).
The extreme values for the OCR2 Register represent special cases when generating a PWM waveform
output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the output will be
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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