Datasheet

A change of the COM21:0 bits state will have effect at the first Compare Match after the bits are written.
For non-PWM modes, the action can be forced to have immediate effect by using the FOC2 strobe bits.
22.7. Modes of Operation
The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined
by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode
(COM21:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform
Generation mode bits do. The COM21:0 bits control whether the PWM output generated should be
inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM21:0 bits control whether
the output should be set, cleared, or toggled at a Compare Match (see Compare Match Output Unit).
For detailed timing information refer to Timer/Counter Timing Diagrams.
22.7.1. Normal Mode
The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction
is always up (incrementing), and no counter clear is performed. The counter simply overruns when it
passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal
operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2
becomes zero. The TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared.
However, combined with the timer overflow interrupt that automatically clears the TOV2 Flag, the timer
resolution can be increased by software. There are no special cases to consider in the Normal mode, a
new counter value can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Output
Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of
the CPU time.
22.7.2. Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the
counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches
the OCR2. The OCR2 defines the top value for the counter, hence also its resolution. This mode allows
greater control of the Compare Match output frequency. It also simplifies the operation of counting
external events.
The timing diagram for the CTC mode is shown in the figure below. The counter value (TCNT2) increases
until a Compare Match occurs between TCNT2 and OCR2, and then counter (TCNT2) is cleared.
Figure 22-5 CTC Mode, Timing Diagram
TCNTn
OCn
(Toggle)
OCn Inte rrupt Flag Se t
1 4
Pe riod
2 3
(COMn1:0 = 1)
Atmel ATmega64A [DATASHEET]
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