Datasheet

11. AVR CPU Core
11.1. Overview
This section discusses the Atmel AVR core architecture in general. The main function of the CPU core is
to ensure correct program execution. The CPU must therefore be able to access memories, perform
calculations, control peripherals, and handle interrupts.
Figure 11-1 Block Diagram of the AVR MCU Architecture
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Line s
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Line s
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addre s s ing
Indire ct Addre s s ing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
i/O Module 2
i/O Module1
i/O Module n
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate
memories and buses for program and data. Instructions in the Program memory are executed with a
single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the
Program memory. This concept enables instructions to be executed in every clock cycle. The Program
memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock
cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU
operation, two operands are output from the Register File, the operation is executed, and the result is
stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space
addressing – enabling efficient address calculations. One of the these address pointers can also be used
as an address pointer for look up tables in Flash Program memory. These added function registers are
the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a
register. Single register operations can also be executed in the ALU. After an arithmetic operation, the
Status Register is updated to reflect information about the result of the operation.
Atmel ATmega64A [DATASHEET]
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