Datasheet

21.11.7. SFIOR – Special Function IO Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: SFIOR
Offset: 0x20
Reset: 0
Property: When addressing I/O Registers as data space the offset address is 0x40
Bit 7 6 5 4 3 2 1 0
TSM PSR0
Access
R/W R/W
Reset 0 0
Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value
that is written to the PSR0 and PSR321 bits is kept, hence keeping the corresponding prescaler reset
signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured
to the same value without the risk of one of them advancing during configuration. When the TSM bit is
written to zero, the PSR0 and PSR321 bits are cleared by hardware, and the Timer/Counters start
counting simultaneously.
Bit 1 – PSR0: Prescaler Reset Timer/Counter0
When this bit is written to one, the Timer/Counter0 prescaler will be reset. The bit will be cleared by
hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always
be read as zero if Timer/Counter0 is clocked by the internal CPU clock. If this bit is written when Timer/
Counter0 is operating in Asynchronous mode, the bit will remain one until the prescaler has been reset.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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