Datasheet

21.11.5. TIMSK – Timer/Counter Interrupt Mask Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: TIMSK
Offset: 0x37
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x57
Bit 7 6 5 4 3 2 1 0
OCIE0 TOIE0
Access
R/W R/W
Reset 0 0
Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable
When the OCIE0 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter0
Compare Match interrupt is enabled. The corresponding interrupt is executed if a Compare Match in
Timer/Counter0 occurs (i.e., when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register –
TIFR).
Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter0
Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0
occurs (i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register – TIFR).
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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