Datasheet

If external pin modes are used for the Timer/Counter2, transitions on the T2 pin will clock the counter
even if the pin is configured as an output. This feature allows software control of the counting.
Bits 6,3 – WGM0n: Waveform Generation Mode [n=0:1]
These bits control the counting sequence of the counter, the source for the maximum (TOP) counter
value, and what type of waveform generation to be used. Modes of operation supported by the Timer/
Counter unit are: Normal mode, Clear Timer on Compare Match (CTC) mode, and two types of Pulse
Width Modulation (PWM) modes. See table below and Modes of Operation.
Table 21-2 Waveform Generation Mode Bit Description
Mode WGM01
(CTC0)
WGM00
(PWM0)
Timer/Counter Mode of Operation
(1)
TOP Update of
OCR0
TOV0 Flag
Set
0 0 0 Normal 0xFF Immediate MAX
1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM
2 1 0 CTC OCR0 Immediate MAX
3 1 1 Fast PWM 0xFF BOTTOM MAX
Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
However, the functionality and location of these bits are compatible with previous versions of the timer.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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