Datasheet

or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in
use or a clock signal is applied to the TOSC1 pin.
• Description of wake up from Power-save or Extended Standby mode when the timer is clocked
asynchronously: When the interrupt condition is met, the wake up process is started on the
following cycle of the timer clock, that is, the timer is always advanced by at least one before the
processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes
the interrupt routine, and resumes execution from the instruction following SLEEP.
• Reading of the TCNT0 Register shortly after wake-up from Power-save may give an incorrect
result. Since TCNT0 is clocked on the asynchronous TOSC clock, reading TCNT0 must be done
through a register synchronized to the internal I/O clock domain. Synchronization takes place for
every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock (clk
I/O
) again
becomes active, TCNT0 will read as the previous value (before entering sleep) until the next rising
TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially
unpredictable, as it depends on the wake-up time. The recommended procedure for reading
TCNT0 is thus as follows:
1. Write any value to either of the registers OCR0 or TCCR0.
2. Wait for the corresponding Update Busy Flag to be cleared.
3. Read TCNT0.
• During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous
timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least
one before the processor can read the timer value causing the setting of the Interrupt Flag. The
Output Compare Pin is changed on the timer clock and is not synchronized to the processor clock.
21.10. Timer/Counter Prescaler
Figure 21-12 Prescaler for Timer/Counter0
10-BIT T/C PRESCALER
TIMER/COUNTER2 CLOCK SOURCE
clk
I/O
clk
T2S
TOS C1
AS2
CS 20
CS 21
CS 22
clk
T2S
/8
clk
T2S
/64
clk
T2S
/128
clk
T2S
/1024
clk
T2S
/256
clk
T2S
/32
0
PS R2
Clea r
clk
T2
The clock source for Timer/Counter0 is named clk
T0S
. clk
T0S
is by default connected to the main system
clock clk
I/O
. By setting the AS0 bit in ASSR, Timer/Counter0 is asynchronously clocked from the TOSC1
pin. This enables use of Timer/Counter0 as a Real Time Counter (RTC). When AS0 is set, pins TOSC1
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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